| /linux-4.4.14/drivers/pci/host/ |
| D | pci-imx6.c | 83 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) in pcie_phy_poll_ack() argument
90 val = readl(dbi_base + PCIE_PHY_STAT); in pcie_phy_poll_ack()
103 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) in pcie_phy_wait_ack() argument
109 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
112 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
114 ret = pcie_phy_poll_ack(dbi_base, 1); in pcie_phy_wait_ack()
119 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack()
121 return pcie_phy_poll_ack(dbi_base, 0); in pcie_phy_wait_ack()
125 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) in pcie_phy_read() argument
130 ret = pcie_phy_wait_ack(dbi_base, addr); in pcie_phy_read()
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| D | pcie-spear13xx.c | 166 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val); in spear13xx_pcie_establish_link()
168 dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val); in spear13xx_pcie_establish_link()
170 dw_pcie_cfg_write(pp->dbi_base + PCI_VENDOR_ID, 2, 0x104A); in spear13xx_pcie_establish_link()
171 dw_pcie_cfg_write(pp->dbi_base + PCI_DEVICE_ID, 2, 0xCD80); in spear13xx_pcie_establish_link()
178 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP, in spear13xx_pcie_establish_link()
183 dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
187 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2, in spear13xx_pcie_establish_link()
192 dw_pcie_cfg_write(pp->dbi_base + exp_cap_off + in spear13xx_pcie_establish_link()
307 struct resource *dbi_base; in spear13xx_pcie_probe() local
341 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); in spear13xx_pcie_probe()
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| D | pci-keystone-dw.c | 325 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_setup_rc_app_regs()
326 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); in ks_dw_pcie_setup_rc_app_regs()
371 return pp->dbi_base; in ks_pcie_cfg_setup()
424 writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
425 writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
433 writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_v3_65_scan_bus()
441 u32 val = readl(pp->dbi_base + DEBUG0); in ks_dw_pcie_link_up()
476 pp->dbi_base = devm_ioremap_resource(pp->dev, res); in ks_dw_pcie_host_init()
477 if (IS_ERR(pp->dbi_base)) in ks_dw_pcie_host_init()
478 return PTR_ERR(pp->dbi_base); in ks_dw_pcie_host_init()
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| D | pcie-designware.h | 28 void __iomem *dbi_base; member
56 void __iomem *dbi_base, u32 *val);
58 u32 val, void __iomem *dbi_base);
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| D | pci-layerscape.c | 217 pp->dbi_base = pcie->dbi; in ls_add_pcie_port()
233 struct resource *dbi_base; in ls_pcie_probe() local
244 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); in ls_pcie_probe()
245 pcie->dbi = devm_ioremap_resource(&pdev->dev, dbi_base); in ls_pcie_probe()
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| D | pcie-designware.c | 115 pp->ops->readl_rc(pp, pp->dbi_base + reg, val); in dw_pcie_readl_rc()
117 *val = readl(pp->dbi_base + reg); in dw_pcie_readl_rc()
123 pp->ops->writel_rc(pp, val, pp->dbi_base + reg); in dw_pcie_writel_rc()
125 writel(val, pp->dbi_base + reg); in dw_pcie_writel_rc()
136 ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); in dw_pcie_rd_own_conf()
149 ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); in dw_pcie_wr_own_conf()
465 if (!pp->dbi_base) { in dw_pcie_host_init()
466 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg->start, in dw_pcie_host_init()
468 if (!pp->dbi_base) { in dw_pcie_host_init()
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| D | pci-keystone.c | 262 pp->dbi_base + PCI_IO_BASE); in ks_pcie_host_init()
265 writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID); in ks_pcie_host_init()
268 val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
272 writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL); in ks_pcie_host_init()
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| D | pci-exynos.c | 436 void __iomem *dbi_base, u32 *val) in exynos_pcie_readl_rc() argument
439 *val = readl(dbi_base); in exynos_pcie_readl_rc()
444 u32 val, void __iomem *dbi_base) in exynos_pcie_writel_rc() argument
447 writel(val, dbi_base); in exynos_pcie_writel_rc()
457 ret = dw_pcie_cfg_read(pp->dbi_base + where, size, val); in exynos_pcie_rd_own_conf()
468 ret = dw_pcie_cfg_write(pp->dbi_base + where, size, val); in exynos_pcie_wr_own_conf()
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| D | pci-dra7xx.c | 90 return readl(pp->dbi_base + offset); in dra7xx_pcie_readl_rc()
96 writel(value, pp->dbi_base + offset); in dra7xx_pcie_writel_rc()
320 pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res)); in dra7xx_add_pcie_port()
321 if (!pp->dbi_base) in dra7xx_add_pcie_port()
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| D | pcie-hisi.c | 172 hisi_pcie->pp.dbi_base = hisi_pcie->reg_base; in hisi_pcie_probe()
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