83 static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)  in pcie_phy_poll_ack()  argument
90 		val = readl(dbi_base + PCIE_PHY_STAT);  in pcie_phy_poll_ack()
103 static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)  in pcie_phy_wait_ack()  argument
109 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
112 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
114 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_wait_ack()
119 	writel(val, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_wait_ack()
121 	return pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_wait_ack()
125 static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)  in pcie_phy_read()  argument
130 	ret = pcie_phy_wait_ack(dbi_base, addr);  in pcie_phy_read()
136 	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_read()
138 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_read()
142 	val = readl(dbi_base + PCIE_PHY_STAT);  in pcie_phy_read()
146 	writel(0x00, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_read()
148 	return pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_read()
151 static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)  in pcie_phy_write()  argument
158 	ret = pcie_phy_wait_ack(dbi_base, addr);  in pcie_phy_write()
163 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
167 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
169 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_write()
175 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
178 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_write()
184 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
187 	ret = pcie_phy_poll_ack(dbi_base, 1);  in pcie_phy_write()
193 	writel(var, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
196 	ret = pcie_phy_poll_ack(dbi_base, 0);  in pcie_phy_write()
200 	writel(0x0, dbi_base + PCIE_PHY_CTRL);  in pcie_phy_write()
233 		val = readl(pp->dbi_base + PCIE_PL_PFLR);  in imx6_pcie_assert_core_reset()
236 		writel(val, pp->dbi_base + PCIE_PL_PFLR);  in imx6_pcie_assert_core_reset()
343 		readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),  in imx6_pcie_wait_for_link()
344 		readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));  in imx6_pcie_wait_for_link()
354 		tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_wait_for_speed_change()
383 	tmp = readl(pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_establish_link()
386 	writel(tmp, pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_establish_link()
397 	tmp = readl(pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_establish_link()
400 	writel(tmp, pp->dbi_base + PCIE_RC_LCR);  in imx6_pcie_establish_link()
406 	tmp = readl(pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_establish_link()
408 	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);  in imx6_pcie_establish_link()
423 	tmp = readl(pp->dbi_base + PCIE_RC_LCSR);  in imx6_pcie_establish_link()
448 	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);  in imx6_pcie_reset_phy()
451 	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);  in imx6_pcie_reset_phy()
455 	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &tmp);  in imx6_pcie_reset_phy()
458 	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, tmp);  in imx6_pcie_reset_phy()
483 		rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);  in imx6_pcie_link_up()
504 	pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid);  in imx6_pcie_link_up()
505 	debug_r0 = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0);  in imx6_pcie_link_up()
565 	struct resource *dbi_base;  in imx6_pcie_probe()  local
579 	dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in imx6_pcie_probe()
580 	pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base);  in imx6_pcie_probe()
581 	if (IS_ERR(pp->dbi_base))  in imx6_pcie_probe()
582 		return PTR_ERR(pp->dbi_base);  in imx6_pcie_probe()