Searched refs:crtc_base (Results 1 - 10 of 10) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| H A D | rv770.c | 804 void rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) rv770_page_flip() argument
816 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); rv770_page_flip()
817 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); rv770_page_flip()
819 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); rv770_page_flip()
820 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base)); rv770_page_flip()
823 (u32)crtc_base); rv770_page_flip()
825 (u32)crtc_base); rv770_page_flip()
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| H A D | radeon_asic.h | 141 u64 crtc_base);
253 u64 crtc_base);
467 void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
537 u64 crtc_base);
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| H A D | rs600.c | 113 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) rs600_page_flip() argument
125 (u32)crtc_base); rs600_page_flip()
127 (u32)crtc_base); rs600_page_flip()
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| H A D | evergreen.c | 1405 * @crtc_base: new address of the crtc (GPU MC address)
1410 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) evergreen_page_flip() argument
1416 upper_32_bits(crtc_base)); evergreen_page_flip()
1418 (u32)crtc_base); evergreen_page_flip()
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| H A D | r100.c | 149 * @crtc_base: new address of the crtc (GPU MC address)
156 void r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base) r100_page_flip() argument
159 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK; r100_page_flip()
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| H A D | radeon.h | 1999 void (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_mode.h | 285 int crtc_id, u64 crtc_base);
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| H A D | dce_v10_0.c | 281 * @crtc_base: new address of the crtc (GPU MC address)
287 int crtc_id, u64 crtc_base) dce_v10_0_page_flip()
293 upper_32_bits(crtc_base)); dce_v10_0_page_flip()
296 lower_32_bits(crtc_base)); dce_v10_0_page_flip()
286 dce_v10_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) dce_v10_0_page_flip() argument
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| H A D | dce_v11_0.c | 271 * @crtc_base: new address of the crtc (GPU MC address)
277 int crtc_id, u64 crtc_base) dce_v11_0_page_flip()
283 upper_32_bits(crtc_base)); dce_v11_0_page_flip()
286 lower_32_bits(crtc_base)); dce_v11_0_page_flip()
276 dce_v11_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) dce_v11_0_page_flip() argument
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| H A D | dce_v8_0.c | 230 * @crtc_base: new address of the crtc (GPU MC address)
236 int crtc_id, u64 crtc_base) dce_v8_0_page_flip()
242 upper_32_bits(crtc_base)); dce_v8_0_page_flip()
245 lower_32_bits(crtc_base)); dce_v8_0_page_flip()
235 dce_v8_0_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base) dce_v8_0_page_flip() argument
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