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Searched refs:clk_register_divider_table (Results 1 – 25 of 25) sorted by relevance

/linux-4.4.14/drivers/clk/sirf/
Dclk-atlas7.c1464 clk = clk_register_divider_table(NULL, "cpupll_div1", "cpupll_vco", 0, in atlas7_clk_init()
1468 clk = clk_register_divider_table(NULL, "cpupll_div2", "cpupll_vco", 0, in atlas7_clk_init()
1472 clk = clk_register_divider_table(NULL, "cpupll_div3", "cpupll_vco", 0, in atlas7_clk_init()
1477 clk = clk_register_divider_table(NULL, "mempll_div1", "mempll_vco", 0, in atlas7_clk_init()
1481 clk = clk_register_divider_table(NULL, "mempll_div2", "mempll_vco", 0, in atlas7_clk_init()
1485 clk = clk_register_divider_table(NULL, "mempll_div3", "mempll_vco", 0, in atlas7_clk_init()
1490 clk = clk_register_divider_table(NULL, "sys0pll_div1", "sys0pll_vco", 0, in atlas7_clk_init()
1494 clk = clk_register_divider_table(NULL, "sys0pll_div2", "sys0pll_vco", 0, in atlas7_clk_init()
1498 clk = clk_register_divider_table(NULL, "sys0pll_div3", "sys0pll_vco", 0, in atlas7_clk_init()
1505 clk = clk_register_divider_table(NULL, "sys1pll_div1", "sys1pll_vco", 0, in atlas7_clk_init()
[all …]
/linux-4.4.14/drivers/clk/
Dclk-clps711x.c121 clk_register_divider_table(NULL, "timer1", "timer_ref", 0, in _clps711x_clk_init()
125 clk_register_divider_table(NULL, "timer2", "timer_ref", 0, in _clps711x_clk_init()
134 clk_register_divider_table(NULL, "spi", "spi_ref", 0, in _clps711x_clk_init()
Dclk-stm32f4.c333 clk_register_divider_table(NULL, "ahb_div", "sys", in stm32f4_rcc_init()
337 clk_register_divider_table(NULL, "apb1_div", "ahb_div", in stm32f4_rcc_init()
343 clk_register_divider_table(NULL, "apb2_div", "ahb_div", in stm32f4_rcc_init()
Dclk-divider.c516 struct clk *clk_register_divider_table(struct device *dev, const char *name, in clk_register_divider_table() function
525 EXPORT_SYMBOL_GPL(clk_register_divider_table);
/linux-4.4.14/drivers/clk/sunxi/
Dclk-sun6i-apb0.c51 clk = clk_register_divider_table(&pdev->dev, clk_name, clk_parent, in sun6i_a31_apb0_clk_probe()
Dclk-sunxi.c877 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0, in sunxi_divider_clk_setup()
/linux-4.4.14/drivers/clk/imx/
Dclk-imx6ul.c193 clks[IMX6UL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, in imx6ul_clocks_init()
195 clks[IMX6UL_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, in imx6ul_clocks_init()
202 clks[IMX6UL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", in imx6ul_clocks_init()
206 clks[IMX6UL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6ul_clocks_init()
208 …clks[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_di… in imx6ul_clocks_init()
Dclk-imx6sl.c271 …clks[IMX6SL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",… in imx6sl_clocks_init()
273 …clks[IMX6SL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",… in imx6sl_clocks_init()
274 …clks[IMX6SL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_di… in imx6sl_clocks_init()
275 …clks[IMX6SL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", … in imx6sl_clocks_init()
Dclk-imx6sx.c231 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, in imx6sx_clocks_init()
234 clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0, in imx6sx_clocks_init()
260 clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", in imx6sx_clocks_init()
264 clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6sx_clocks_init()
266 …clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_di… in imx6sx_clocks_init()
Dclk-imx6q.c231 clk[IMX6QDL_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0, in imx6q_clocks_init()
272 …clk[IMX6QDL_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", C… in imx6q_clocks_init()
274 …clk[IMX6QDL_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", C… in imx6q_clocks_init()
275 …clk[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_di… in imx6q_clocks_init()
Dclk-vf610.c233 …clk[VF610_CLK_PLL4_MAIN_DIV] = clk_register_divider_table(NULL, "pll4_audio_div", "pll4_audio", 0,… in vf610_clocks_init()
/linux-4.4.14/drivers/clk/shmobile/
Dclk-r8a7740.c141 return clk_register_divider_table(NULL, name, parent_name, 0, in r8a7740_cpg_register_clock()
Dclk-sh73a0.c158 return clk_register_divider_table(NULL, name, parent_name, 0, in sh73a0_cpg_register_clock()
Dclk-r8a73a4.c186 return clk_register_divider_table(NULL, name, parent_name, 0, in r8a73a4_cpg_register_clock()
Dclk-rcar-gen2.c362 return clk_register_divider_table(NULL, name, parent_name, 0, in rcar_gen2_cpg_register_clock()
/linux-4.4.14/drivers/clk/tegra/
Dclk-divider.c197 return clk_register_divider_table(NULL, name, parent_name, 0, reg, in tegra_clk_register_mc()
Dclk-tegra114.c1154 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, in tegra114_pll_init()
Dclk-tegra124.c1268 clk = clk_register_divider_table(NULL, "pll_re_out", "pll_re_vco", 0, in tegra124_pll_init()
/linux-4.4.14/drivers/clk/hisilicon/
Dclk.c153 clk = clk_register_divider_table(NULL, clks[i].name, in hisi_clk_register_divider()
/linux-4.4.14/drivers/clk/rockchip/
Dclk.c243 clk = clk_register_divider_table(NULL, in rockchip_clk_register_branches()
/linux-4.4.14/drivers/clk/samsung/
Dclk.c229 clk = clk_register_divider_table(NULL, list->name, in samsung_clk_register_div()
/linux-4.4.14/include/linux/
Dclk-provider.h403 struct clk *clk_register_divider_table(struct device *dev, const char *name,
/linux-4.4.14/drivers/clk/zte/
Dclk-zx296702.c203 return clk_register_divider_table(NULL, name, parent, 0, reg, shift, in zx_divtbl()
/linux-4.4.14/drivers/clk/st/
Dclkgen-mux.c516 clk = clk_register_divider_table(NULL, clk_name, parent_name, in st_of_clkgena_prediv_setup()
/linux-4.4.14/arch/powerpc/platforms/512x/
Dclock-commonclk.c254 return clk_register_divider_table(NULL, name, parent_name, 0, in mpc512x_clk_divtable()