Searched refs:clk_mask (Results 1 - 19 of 19) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dseq.h10 #define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) macro
H A Dnv50.c446 clk_mask(hwsq, mast, mastm, 0x00000000); nv50_clk_calc()
447 clk_mask(hwsq, divs, divsm, divsv); nv50_clk_calc()
448 clk_mask(hwsq, mast, mastm, mastv); nv50_clk_calc()
454 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); nv50_clk_calc()
456 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); nv50_clk_calc()
463 clk_mask(hwsq, nvpll[0], 0xc03f0100, nv50_clk_calc()
465 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); nv50_clk_calc()
474 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16)); nv50_clk_calc()
475 clk_mask(hwsq, mast, 0x00100033, 0x00000023); nv50_clk_calc()
481 clk_mask(hwsq, spll[0], 0xc03f0100, nv50_clk_calc()
483 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); nv50_clk_calc()
484 clk_mask(hwsq, mast, 0x00100033, 0x00000033); nv50_clk_calc()
/linux-4.4.14/arch/ia64/kernel/
H A Dfsyscall_gtod_data.h12 cycle_t clk_mask; member in struct:fsyscall_gtod_data_t
H A Dasm-offsets.c276 offsetof (struct fsyscall_gtod_data_t, clk_mask)); foo()
H A Dtime.c405 fsyscall_gtod_data.clk_mask = c->mask; update_vsyscall_old()
/linux-4.4.14/drivers/clk/sunxi/
H A Dclk-usb.c91 u32 clk_mask; member in struct:usb_clk_data
118 qty = find_last_bit((unsigned long *)&data->clk_mask, sunxi_usb_clk_setup()
131 for_each_set_bit(i, (unsigned long *)&data->clk_mask, sunxi_usb_clk_setup()
174 .clk_mask = BIT(8) | BIT(7) | BIT(6),
187 .clk_mask = BIT(8) | BIT(6),
198 .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
209 .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8),
220 .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
234 .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
/linux-4.4.14/arch/cris/include/uapi/asm/
H A Detraxgpio.h65 msb, data_mask[7:0] , clk_mask[7:0]
68 #define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
69 ( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
/linux-4.4.14/drivers/gpu/drm/msm/edp/
H A Dedp_ctrl.c202 static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) edp_clk_enable() argument
206 DBG("mask=%x", clk_mask); edp_clk_enable()
208 if (clk_mask & EDP_CLK_MASK_AHB) { edp_clk_enable()
215 if (clk_mask & EDP_CLK_MASK_AUX) { edp_clk_enable()
228 if (clk_mask & EDP_CLK_MASK_LINK) { edp_clk_enable()
245 if (clk_mask & EDP_CLK_MASK_PIXEL) { edp_clk_enable()
262 if (clk_mask & EDP_CLK_MASK_MDP_CORE) { edp_clk_enable()
273 if (clk_mask & EDP_CLK_MASK_PIXEL) edp_clk_enable()
276 if (clk_mask & EDP_CLK_MASK_LINK) edp_clk_enable()
279 if (clk_mask & EDP_CLK_MASK_AUX) edp_clk_enable()
282 if (clk_mask & EDP_CLK_MASK_AHB) edp_clk_enable()
288 static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) edp_clk_disable() argument
290 if (clk_mask & EDP_CLK_MASK_MDP_CORE) edp_clk_disable()
292 if (clk_mask & EDP_CLK_MASK_PIXEL) edp_clk_disable()
294 if (clk_mask & EDP_CLK_MASK_LINK) edp_clk_disable()
296 if (clk_mask & EDP_CLK_MASK_AUX) edp_clk_disable()
298 if (clk_mask & EDP_CLK_MASK_AHB) edp_clk_disable()
/linux-4.4.14/arch/cris/arch-v10/drivers/
H A Dgpio.c63 unsigned char clk_mask; member in struct:gpio_private
251 *priv->port = *priv->shadow &= ~(priv->clk_mask); gpio_write_bit()
258 *priv->port = *priv->shadow |= priv->clk_mask; gpio_write_bit()
290 if (priv->clk_mask == 0 || priv->data_mask == 0) { gpio_write()
297 count, priv->data_mask, priv->clk_mask, priv->write_msb)); gpio_write()
346 priv->clk_mask = 0; gpio_open()
629 priv->clk_mask = arg & 0xFF; gpio_ioctl()
635 if (!((priv->clk_mask & priv->changeable_bits) && gpio_ioctl()
637 (priv->clk_mask & *priv->dir_shadow) && gpio_ioctl()
640 priv->clk_mask = 0; gpio_ioctl()
/linux-4.4.14/sound/pci/ice1712/
H A Dak4xxx.c91 tmp &= ~priv->clk_mask; snd_ice1712_akm4xxx_write()
102 tmp |= priv->clk_mask; snd_ice1712_akm4xxx_write()
H A Drevo.c251 .clk_mask = VT1724_REVO_CCLK,
273 .clk_mask = VT1724_REVO_CCLK,
294 .clk_mask = VT1724_REVO_CCLK,
312 .clk_mask = VT1724_REVO_CCLK,
362 .clk_mask = VT1724_REVO_CCLK,
H A Ddelta.c461 .clk_mask = ICE1712_DELTA_AP_CCLK,
482 .clk_mask = ICE1712_DELTA_AP_CCLK,
504 .clk_mask = ICE1712_DELTA_1010LT_CCLK,
526 .clk_mask = ICE1712_DELTA_66E_CCLK,
549 .clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK,
571 .clk_mask = ICE1712_VX442_CCLK,
H A Dhoontech.c285 .clk_mask = ICE1712_STDSP24_SERIAL_CLOCK, snd_ice1712_value_init()
H A Dews.c361 .clk_mask = ICE1712_EWS88_SERIAL_CLOCK,
382 .clk_mask = ICE1712_EWS88_SERIAL_CLOCK,
403 .clk_mask = ICE1712_6FIRE_SERIAL_CLOCK,
H A Dice1712.h268 unsigned int clk_mask; /* CLK gpio bit */ member in struct:snd_ak4xxx_private
H A Dphase.c115 .clk_mask = 1 << 5,
/linux-4.4.14/drivers/spi/
H A Dspi-ti-qspi.c130 u32 clk_ctrl_reg, clk_rate, clk_mask; ti_qspi_setup() local
174 clk_mask = QSPI_CLK_EN | clk_div; ti_qspi_setup()
175 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); ti_qspi_setup()
176 ctx_reg->clkctrl = clk_mask; ti_qspi_setup()
/linux-4.4.14/include/linux/
H A Dfs_enet_pd.h128 u32 clk_mask; member in struct:fs_platform_info
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_combios.c417 u32 clk_mask, combios_setup_i2c_bus()
521 if (clk_mask && data_mask) { combios_setup_i2c_bus()
523 i2c.mask_clk_mask = clk_mask; combios_setup_i2c_bus()
525 i2c.a_clk_mask = clk_mask; combios_setup_i2c_bus()
527 i2c.en_clk_mask = clk_mask; combios_setup_i2c_bus()
529 i2c.y_clk_mask = clk_mask; combios_setup_i2c_bus()
415 combios_setup_i2c_bus(struct radeon_device *rdev, enum radeon_combios_ddc ddc, u32 clk_mask, u32 data_mask) combios_setup_i2c_bus() argument

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