/linux-4.4.14/drivers/clk/ti/ |
D | clockdomain.c | 51 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm() 57 clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm() 61 __func__, clk_hw_get_name(hw)); in omap2_clkops_enable_clkdm() 67 __func__, clk_hw_get_name(hw), clk->clkdm_name, ret); in omap2_clkops_enable_clkdm() 89 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm() 95 clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm() 99 __func__, clk_hw_get_name(hw)); in omap2_clkops_disable_clkdm()
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D | clkt_dflt.c | 113 idlest_val, clk_hw_get_name(&clk->hw)); in _omap2_module_wait_ready() 219 __func__, clk_hw_get_name(hw), in omap2_dflt_clk_enable() 227 clk_hw_get_name(hw)); in omap2_dflt_clk_enable() 273 __func__, clk_hw_get_name(hw)); in omap2_dflt_clk_disable()
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D | dpll3xxx.c | 72 clk_name = clk_hw_get_name(&clk->hw); in _omap3_wait_dpll_status() 148 pr_debug("clock: locking DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_lock() 196 clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_bypass() 226 pr_debug("clock: stopping DPLL %s\n", clk_hw_get_name(&clk->hw)); in _omap3_noncore_dpll_stop() 432 __func__, clk_hw_get_name(hw), in omap3_noncore_dpll_enable() 569 clk_hw_get_name(hw), rate); in omap3_noncore_dpll_set_rate()
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D | apll.c | 53 clk_name = clk_hw_get_name(&clk->hw); in dra7_apll_enable() 276 clk_hw_get_name(&clk->hw)); in omap2_apll_enable()
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D | clkt_dpll.c | 305 clk_name = clk_hw_get_name(hw); in omap2_dpll_round_rate()
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D | divider.c | 112 clk_hw_get_name(hw)); in ti_clk_divider_recalc_rate()
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/linux-4.4.14/drivers/clk/ux500/ |
D | clk-prcmu.c | 46 clk_hw_get_name(hw)); in clk_prcmu_unprepare() 104 (char *)clk_hw_get_name(hw), in clk_prcmu_opp_prepare() 108 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_prepare() 117 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_prepare() 132 clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare() 138 (char *)clk_hw_get_name(hw)); in clk_prcmu_opp_unprepare() 154 __func__, clk_hw_get_name(hw)); in clk_prcmu_opp_volt_prepare() 177 clk_hw_get_name(hw)); in clk_prcmu_opp_volt_unprepare()
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D | clk-sysctrl.c | 55 __func__, clk_hw_get_name(hw)); in clk_sysctrl_unprepare()
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/linux-4.4.14/drivers/clk/ |
D | clk-xgene.c | 76 pr_debug("%s pll %s\n", clk_hw_get_name(hw), in xgene_clk_pll_is_enabled() 114 pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw), in xgene_clk_pll_recalc_rate() 227 pr_debug("%s clock enabled\n", clk_hw_get_name(hw)); in xgene_clk_enable() 236 clk_hw_get_name(hw), ®, in xgene_clk_enable() 247 clk_hw_get_name(hw), ®, in xgene_clk_enable() 268 pr_debug("%s clock disabled\n", clk_hw_get_name(hw)); in xgene_clk_disable() 294 pr_debug("%s clock checking\n", clk_hw_get_name(hw)); in xgene_clk_is_enabled() 297 pr_debug("%s clock is %s\n", clk_hw_get_name(hw), in xgene_clk_is_enabled() 320 clk_hw_get_name(hw), in xgene_clk_recalc_rate() 326 clk_hw_get_name(hw), parent_rate, parent_rate); in xgene_clk_recalc_rate() [all …]
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D | clk-si5351.c | 442 __func__, clk_hw_get_name(hw), in si5351_pll_recalc_rate() 500 __func__, clk_hw_get_name(hw), a, b, c, in si5351_pll_round_rate() 524 __func__, clk_hw_get_name(hw), in si5351_pll_set_rate() 635 __func__, clk_hw_get_name(hw), in si5351_msynth_recalc_rate() 748 __func__, clk_hw_get_name(hw), a, b, c, divby4, in si5351_msynth_round_rate() 780 __func__, clk_hw_get_name(hw), in si5351_msynth_set_rate() 1045 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_round_rate() 1096 __func__, clk_hw_get_name(hw), (1 << rdiv), in si5351_clkout_set_rate()
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D | clk-divider.c | 131 clk_hw_get_name(hw)); in divider_recalc_rate()
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D | clk.c | 281 const char *clk_hw_get_name(const struct clk_hw *hw) in clk_hw_get_name() function 285 EXPORT_SYMBOL_GPL(clk_hw_get_name);
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/linux-4.4.14/drivers/clk/berlin/ |
D | berlin2-pll.c | 64 pr_warn("%s has zero rfdiv\n", clk_hw_get_name(hw)); in berlin2_pll_recalc_rate() 73 clk_hw_get_name(hw), vcodivsel); in berlin2_pll_recalc_rate()
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/linux-4.4.14/drivers/clk/rockchip/ |
D | clk-pll.c | 160 clk_hw_get_name(hw)); in rockchip_rk3066_pll_recalc_rate() 247 __func__, clk_hw_get_name(hw), old_rate, drate, prate); in rockchip_rk3066_pll_set_rate() 253 drate, clk_hw_get_name(hw)); in rockchip_rk3066_pll_set_rate() 307 __func__, clk_hw_get_name(hw), drate, rate->nr, cur.nr, in rockchip_rk3066_pll_init() 317 __func__, clk_hw_get_name(hw)); in rockchip_rk3066_pll_init()
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D | clk-inverter.c | 53 __func__, degrees, clk_hw_get_name(hw)); in rockchip_inv_set_phase()
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D | clk-mmc-phase.c | 129 clk_hw_get_name(hw), degrees, delay_num, in rockchip_mmc_set_phase()
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/linux-4.4.14/drivers/clk/st/ |
D | clkgen-fsyn.c | 516 clk_hw_get_name(hw), __func__); in quadfs_pll_fs660c32_recalc_rate() 561 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_round_rate() 584 __func__, clk_hw_get_name(hw), in quadfs_pll_fs660c32_set_rate() 748 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_enable() 773 pr_debug("%s: %s\n", __func__, clk_hw_get_name(hw)); in quadfs_fsynth_disable() 790 __func__, clk_hw_get_name(hw), nsb); in quadfs_fsynth_is_enabled() 949 clk_hw_get_name(hw), __func__); in quadfs_recalc_rate() 952 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in quadfs_recalc_rate() 965 __func__, clk_hw_get_name(hw), in quadfs_round_rate()
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D | clk-flexgen.c | 48 pr_debug("%s: flexgen output enabled\n", clk_hw_get_name(hw)); in flexgen_enable() 62 pr_debug("%s: flexgen output disabled\n", clk_hw_get_name(hw)); in flexgen_disable()
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D | clkgen-pll.c | 434 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in recalc_stm_pll800c65() 459 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in recalc_stm_pll1600c65() 542 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in recalc_stm_pll3200c32() 633 pr_debug("%s:%s rate %lu\n", clk_hw_get_name(hw), __func__, rate); in recalc_stm_pll1200c32()
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D | clkgen-mux.c | 143 __func__, clk_hw_get_name(hw)); in clkgena_divmux_get_parent()
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/linux-4.4.14/drivers/clk/samsung/ |
D | clk-pll.c | 185 drate, clk_hw_get_name(hw)); in samsung_pll35xx_set_rate() 293 drate, clk_hw_get_name(hw)); in samsung_pll36xx_set_rate() 408 drate, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate() 460 __func__, clk_hw_get_name(hw)); in samsung_pll45xx_set_rate() 559 drate, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate() 619 __func__, clk_hw_get_name(hw)); in samsung_pll46xx_set_rate() 777 drate, clk_hw_get_name(hw)); in samsung_s3c2410_pll_set_rate() 1018 drate, clk_hw_get_name(hw)); in samsung_pll2550xx_set_rate() 1116 drate, clk_hw_get_name(hw)); in samsung_pll2650xx_set_rate()
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/linux-4.4.14/drivers/clk/qcom/ |
D | clk-branch.c | 78 const char *name = clk_hw_get_name(&br->clkr.hw); in clk_branch_wait()
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D | clk-rcg2.c | 83 __func__, clk_hw_get_name(hw)); in clk_rcg2_get_parent() 92 const char *name = clk_hw_get_name(hw); in update_config() 306 const char *name = clk_hw_get_name(hw); in clk_rcg2_shared_force_enable()
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D | clk-pll.c | 197 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
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D | clk-rcg.c | 62 __func__, clk_hw_get_name(hw)); in clk_rcg_get_parent() 98 __func__, clk_hw_get_name(hw)); in clk_dyn_rcg_get_parent()
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/linux-4.4.14/drivers/clk/pistachio/ |
D | clk-pll.c | 203 const char *name = clk_hw_get_name(hw); in pll_gf40lp_frac_set_rate() 360 const char *name = clk_hw_get_name(hw); in pll_gf40lp_laint_set_rate()
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/linux-4.4.14/drivers/clk/shmobile/ |
D | clk-div6.c | 142 __func__, clk_hw_get_name(hw), hw_index); in cpg_div6_clock_get_parent()
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/linux-4.4.14/drivers/clk/bcm/ |
D | clk-bcm2835.c | 923 clk_hw_get_name(hw)); in bcm2835_pll_on() 963 clk_hw_get_name(hw), rate, in bcm2835_pll_set_rate() 1247 clk_hw_get_name(&clock->hw)); in bcm2835_clock_wait_busy()
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/linux-4.4.14/drivers/clk/tegra/ |
D | clk-pll.c | 267 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock() 598 __func__, clk_hw_get_name(hw), in clk_pll_set_rate() 608 clk_hw_get_name(hw), rate); in clk_pll_set_rate() 666 clk_hw_get_name(hw)); in clk_pll_recalc_rate()
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/linux-4.4.14/include/linux/ |
D | clk-provider.h | 647 const char *clk_hw_get_name(const struct clk_hw *hw);
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/linux-4.4.14/drivers/clk/mmp/ |
D | clk-mix.c | 184 __func__, clk_hw_get_name(&mix->hw)); in _set_rate()
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