Home
last modified time | relevance | path

Searched refs:cdclk (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/clk/samsung/
Dclk-s5pv210-audss.c74 struct clk *hclk, *pll_ref, *pll_in, *cdclk, *sclk_audio; in s5pv210_audss_clk_probe() local
111 cdclk = devm_clk_get(&pdev->dev, "iiscdclk0"); in s5pv210_audss_clk_probe()
125 if (!IS_ERR(cdclk)) in s5pv210_audss_clk_probe()
126 mout_i2s_p[1] = __clk_get_name(cdclk); in s5pv210_audss_clk_probe()
Dclk-exynos-audss.c114 struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio, *sclk_pcm_in; in exynos_audss_clk_probe() local
167 cdclk = devm_clk_get(&pdev->dev, "cdclk"); in exynos_audss_clk_probe()
169 if (!IS_ERR(cdclk)) in exynos_audss_clk_probe()
170 mout_i2s_p[1] = __clk_get_name(cdclk); in exynos_audss_clk_probe()
/linux-4.4.14/Documentation/devicetree/bindings/clock/
Dclk-exynos-audss.txt24 - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
32 "pll_in", "cdclk", "sclk_audio", and "sclk_pcm_in" respectively.
74 clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in", "cdclk";
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_display.c5367 unsigned int cdclk = to_intel_atomic_state(state)->cdclk; in modeset_update_crtc_power_domains() local
5369 if (cdclk != dev_priv->cdclk_freq && in modeset_update_crtc_power_domains()
5862 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) in valleyview_set_cdclk() argument
5870 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ in valleyview_set_cdclk()
5872 else if (cdclk == 266667) in valleyview_set_cdclk()
5891 if (cdclk == 400000) { in valleyview_set_cdclk()
5894 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; in valleyview_set_cdclk()
5916 if (cdclk == 400000) in valleyview_set_cdclk()
5927 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) in cherryview_set_cdclk() argument
5935 switch (cdclk) { in cherryview_set_cdclk()
[all …]
Dintel_drv.h250 unsigned int cdclk; member
/linux-4.4.14/arch/arm/boot/dts/
Ds3c64xx-pinctrl.dtsi339 i2s0_cdclk: i2s0-cdclk {
351 i2s1_cdclk: i2s1-cdclk {
365 i2s2_cdclk: i2s2-cdclk {