5367 		unsigned int cdclk = to_intel_atomic_state(state)->cdclk;  in modeset_update_crtc_power_domains()  local
5369 		if (cdclk != dev_priv->cdclk_freq &&  in modeset_update_crtc_power_domains()
5862 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)  in valleyview_set_cdclk()  argument
5870 	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */  in valleyview_set_cdclk()
5872 	else if (cdclk == 266667)  in valleyview_set_cdclk()
5891 	if (cdclk == 400000) {  in valleyview_set_cdclk()
5894 		divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;  in valleyview_set_cdclk()
5916 	if (cdclk == 400000)  in valleyview_set_cdclk()
5927 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)  in cherryview_set_cdclk()  argument
5935 	switch (cdclk) {  in cherryview_set_cdclk()
5942 		MISSING_CASE(cdclk);  in cherryview_set_cdclk()
5951 	cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;  in cherryview_set_cdclk()
6051 	to_intel_atomic_state(state)->cdclk =  in valleyview_modeset_calc_cdclk()
6066 	to_intel_atomic_state(state)->cdclk =  in broxton_modeset_calc_cdclk()
6111 	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;  in valleyview_modeset_commit_cdclk()
6752 	int cdclk;  in broxton_get_display_clock_speed()  local
6757 	cdclk = 19200 * pll_ratio / 2;  in broxton_get_display_clock_speed()
6761 		return cdclk;  /* 576MHz or 624MHz */  in broxton_get_display_clock_speed()
6763 		return cdclk * 2 / 3; /* 384MHz */  in broxton_get_display_clock_speed()
6765 		return cdclk / 2; /* 288MHz */  in broxton_get_display_clock_speed()
6767 		return cdclk / 4; /* 144MHz */  in broxton_get_display_clock_speed()
9568 	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;  in broxton_modeset_commit_cdclk()
9602 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)  in broadwell_set_cdclk()  argument
9636 	switch (cdclk) {  in broadwell_set_cdclk()
9674 	WARN(cdclk != dev_priv->cdclk_freq,  in broadwell_set_cdclk()
9676 	     cdclk, dev_priv->cdclk_freq);  in broadwell_set_cdclk()
9683 	int cdclk;  in broadwell_modeset_calc_cdclk()  local
9690 		cdclk = 675000;  in broadwell_modeset_calc_cdclk()
9692 		cdclk = 540000;  in broadwell_modeset_calc_cdclk()
9694 		cdclk = 450000;  in broadwell_modeset_calc_cdclk()
9696 		cdclk = 337500;  in broadwell_modeset_calc_cdclk()
9702 	if (cdclk > dev_priv->max_cdclk_freq) {  in broadwell_modeset_calc_cdclk()
9704 			  cdclk, dev_priv->max_cdclk_freq);  in broadwell_modeset_calc_cdclk()
9705 		cdclk = dev_priv->max_cdclk_freq;  in broadwell_modeset_calc_cdclk()
9708 	to_intel_atomic_state(state)->cdclk = cdclk;  in broadwell_modeset_calc_cdclk()
9716 	unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;  in broadwell_modeset_commit_cdclk()
13077 		unsigned int cdclk;  in intel_modeset_checks()  local
13081 		cdclk = to_intel_atomic_state(state)->cdclk;  in intel_modeset_checks()
13082 		if (!ret && cdclk != dev_priv->cdclk_freq)  in intel_modeset_checks()
13088 		to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;  in intel_modeset_checks()
13173 		to_intel_atomic_state(state)->cdclk =  in intel_atomic_check()
13515 	int crtc_clock, cdclk;  in skl_max_scale()  local
13523 	cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;  in skl_max_scale()
13525 	if (!crtc_clock || !cdclk)  in skl_max_scale()
13534 	max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));  in skl_max_scale()