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/linux-4.4.14/Documentation/block/
Dwriteback_cache_control.txt9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
D00-INDEX28 - Control of volatile write back caches
Dbiodoc.txt102 Sophisticated devices with large built-in caches, intelligent i/o scheduling
/linux-4.4.14/arch/arm/boot/compressed/
Dhead-xscale.S27 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
29 @ disabling MMU and caches
/linux-4.4.14/arch/arm/mm/
Dproc-arm720.S60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
122 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
150 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
Dproc-sa110.S52 mcr p15, 0, r0, c1, c0, 0 @ disable caches
68 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
165 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
Dproc-fa526.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
63 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
142 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm926.S67 mcr p15, 0, r0, c1, c0, 0 @ disable caches
83 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
418 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
431 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
439 mov r0, #4 @ disable write-back on caches explicitly
Dproc-sa1100.S60 mcr p15, 0, r0, c1, c0, 0 @ disable caches
76 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
204 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm920.S75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
403 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
416 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-mohawk.S57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
75 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
370 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
389 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
Dproc-arm740.S44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
66 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
Dproc-arm925.S98 mcr p15, 0, r0, c1, c0, 0 @ disable caches
123 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
450 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
457 mov r0, #4 @ disable write-back on caches explicitly
Dproc-arm922.S77 mcr p15, 0, r0, c1, c0, 0 @ disable caches
93 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
394 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1020e.S83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
429 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1026.S74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-arm1022.S74 mcr p15, 0, r0, c1, c0, 0 @ disable caches
90 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
413 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-xsc3.S95 mcr p15, 0, r0, c1, c0, 0 @ disable caches
116 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
433 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
453 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
Dproc-arm1020.S83 mcr p15, 0, r0, c1, c0, 0 @ disable caches
99 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
447 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-feroceon.S88 mcr p15, 0, r0, c1, c0, 0 @ disable caches
104 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
533 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
546 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
Dproc-xscale.S130 mcr p15, 0, r0, c1, c0, 0 @ disable caches
158 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
549 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
563 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
Dpv-fixup-asm.S26 bic ip, r8, #CR_M @ disable caches and MMU
Dproc-v6.S45 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Dproc-arm940.S43 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Dproc-arm946.S50 mcr p15, 0, r0, c1, c0, 0 @ disable caches
Dproc-v7.S36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
DKconfig103 instruction and data caches. It is used in Altera's
122 different instruction and data caches. It is used in TI's OMAP
/linux-4.4.14/drivers/staging/android/
DTODO19 which want to manage caches themselves and which indicates whether cpu caches
/linux-4.4.14/Documentation/filesystems/nfs/
Drpc-cache.txt8 a wide variety of values to be caches.
10 There are a number of caches that are similar in structure though
12 of common code for managing these caches.
14 Examples of caches that are likely to be needed are:
92 includes it on a list of caches that will be regularly
Dpnfs.txt4 The are several inter-related caches. We have layouts which can
/linux-4.4.14/drivers/scsi/qla2xxx/
DKconfig25 Upon request, the driver caches the firmware image until
/linux-4.4.14/drivers/staging/lustre/lustre/obdclass/
Dlu_object.c1920 int lu_kmem_init(struct lu_kmem_descr *caches) in lu_kmem_init() argument
1923 struct lu_kmem_descr *iter = caches; in lu_kmem_init()
1932 lu_kmem_fini(caches); in lu_kmem_init()
1944 void lu_kmem_fini(struct lu_kmem_descr *caches) in lu_kmem_fini() argument
1946 for (; caches->ckd_cache != NULL; ++caches) { in lu_kmem_fini()
1947 kmem_cache_destroy(*caches->ckd_cache); in lu_kmem_fini()
1948 *caches->ckd_cache = NULL; in lu_kmem_fini()
/linux-4.4.14/tools/testing/selftests/zram/
DREADME9 use as swap disks, various caches under /var and maybe many more :)
/linux-4.4.14/fs/coda/
DKconfig11 persistent client caches and write back caching.
/linux-4.4.14/Documentation/
Dpercpu-rw-semaphore.txt9 is bouncing between L1 caches of the cores, causing performance
Dcachetlb.txt130 us to properly handle systems whose caches are strict and require
138 indexed caches which must be flushed when virtual-->physical
140 indexed physically tagged caches of IA32 processors have no need to
141 implement these interfaces since the caches are fully synchronized
149 the caches. That is, after running, there will be no cache
158 the caches. That is, after running, there will be no cache
165 optimizations for VIPT caches.
Ddma-buf-sharing.txt246 1. Prepare access, which invalidate any necessary caches and make the object
249 3. Finish access, which will flush any necessary cpu caches and free reserved
392 leaving the cpu domain and flushing caches at fault time. Note that all the
448 - If an exporter needs to manually flush caches and hence needs to fake
DDMA-attributes.txt81 to 'device' domain, what synchronizes CPU caches for the given region
Dmemory-barriers.txt559 machines with split caches, so that, for example, one cache bank processes
2595 a certain extent by the caches that lie between CPUs and memory, and by the
2599 caches goes, the memory system has to include the CPU's caches, and memory
2655 caches are expected to be coherent, there's no guarantee that that coherency
2662 has a pair of parallel data caches (CPU 1 has A/B, and CPU 2 has C/D):
2704 between them to guarantee that they will appear to reach that CPU's caches in
2718 the local CPU's caches have apparently been updated in the correct order. But
2728 cacheline holding p may get updated in one of the second CPU's caches whilst
2730 CPU's caches by some other cache event:
2780 Other CPUs may also have split caches, but must coordinate between the various
[all …]
Dbcache.txt76 Cache devices are managed as sets; multiple caches per set isn't supported yet
425 purposes (i.e. testing how different size caches affect your hit rate), but
Drobust-futexes.txt67 destroying the CPU's L1 and L2 caches!
Dkmemcheck.txt203 kmemcheck in such a way that the slab caches which are under SLUB debugging
211 slab cache, and with kmemcheck tracking all the other caches. This is advanced
Dmemory-hotplug.txt303 page caches. For offlining a memory block by migration, the kernel has to
DDMA-API-HOWTO.txt135 sharing problems (data corruption) on CPUs with DMA-incoherent caches.
376 Also, systems with caches that aren't DMA-coherent will work better
Dedac.txt40 Some architectures have ECC detectors for L1, L2 and L3 caches,
Dkernel-parameters.txt2389 caches in the slab allocator. Saves per-node memory,
/linux-4.4.14/arch/unicore32/mm/
Dproc-ucv2.S49 movc p0.c1, ip, #0 @ disable caches and mmu
/linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/
Dpamu.txt63 second is the number of "ways". For direct-mapped caches,
69 second is the number of "ways". For direct-mapped caches,
/linux-4.4.14/Documentation/arm64/
Dbooting.txt157 coherent masters with caches enabled, this will typically require
159 System caches which respect the architected cache maintenance by VA
161 System caches which do not respect architected cache maintenance by VA
198 The requirements described above for CPU mode, caches, MMUs, architected
/linux-4.4.14/Documentation/hwmon/
Dadc128d81838 caches the alarm status for each sensor until it is at least reported
Dlm7577 The driver caches the values for a period varying between 1 second for the
/linux-4.4.14/tools/perf/Documentation/
Dperf-buildid-cache.txt43 Purge all cached binaries including older caches which have specified
/linux-4.4.14/fs/fscache/
DKconfig7 Different sorts of caches can be plugged in, depending on the
/linux-4.4.14/Documentation/filesystems/
D9p.txt71 cache=mode specifies a caching policy. By default, no caches are used.
134 /sys/fs/9p/caches. (applies only to cache=fscache)
Ddax.txt89 mapped caches such as ARM, MIPS and SPARC.
Dsquashfs.txt168 larger), the code implements an index cache that caches the mapping from
244 recently accessed data Squashfs uses two small metadata and fragment caches.
Dtmpfs.txt8 tmpfs puts everything into the kernel internal caches and grows and
Dramfs-rootfs-initramfs.txt45 unnecessary work for the CPU, and pollutes the CPU caches. (There are tricks
49 since all file access goes through the page and dentry caches. The RAM
Doverlayfs.txt111 will each have separate caches. A seekdir to the start of the
Dext4.txt191 of journal commits, making volatile disk write caches
Dproc.txt902 SReclaimable: Part of Slab, that might be reclaimed, such as caches
/linux-4.4.14/Documentation/vm/
Dslub.txt6 slab caches. SLUB always includes full debugging but it is off by default.
45 O Switch debugging off for caches that would have
66 a result of storing the metadata (for example, caches with PAGE_SIZE object
69 switch off debugging for such caches by default, use
Dnuma26 is handled in hardware by the processor caches and/or the system interconnect.
Dcleancache.txt272 memory hungry caches like web browsers. (Jamie Lokier)
/linux-4.4.14/drivers/staging/lustre/lustre/include/
Dlu_object.h1299 int lu_kmem_init(struct lu_kmem_descr *caches);
1300 void lu_kmem_fini(struct lu_kmem_descr *caches);
/linux-4.4.14/security/keys/
DKconfig46 (for example Kerberos ticket caches). The data may be stored out to
/linux-4.4.14/arch/unicore32/kernel/
Dsleep.S172 movc p0.c5, r1, #28 @ invalidate I & D caches, BTB
/linux-4.4.14/Documentation/powerpc/
Dcpu_features.txt10 split instruction and data caches, and if the CPU supports the DOZE and NAP
/linux-4.4.14/arch/frv/kernel/
Dcmode.S111 # (5) Flush the content of all caches by the DCEF instruction.
Dhead.S48 # invalidate and disable both of the caches and turn off the memory access checking
/linux-4.4.14/fs/cachefiles/
Dbind.c25 static int cachefiles_daemon_add_cache(struct cachefiles_cache *caches);
/linux-4.4.14/arch/nios2/platform/
DKconfig.platform104 perfectly fine, even if the Nios II is configured with smaller caches.
/linux-4.4.14/Documentation/mmc/
Dmmc-async-req.txt13 possible to prepare the caches for next job in parallel with an active
/linux-4.4.14/Documentation/ABI/testing/
Dsysfs-devices-system-cpu177 All AMD processors with L3 caches provide this functionality.
262 - Data: cache that only caches data
Dsysfs-kernel-slab19 The aliases file is read-only and specifies how many caches
424 caches that do not.
/linux-4.4.14/Documentation/arm/
Dcluster-pm-race-avoidance.txt35 writing some hardware registers and invalidating large caches), other
190 caches).
350 down, for example by cleaning data caches and exiting
Dvlocks.txt169 unable to enable their caches yet. This means that the
/linux-4.4.14/arch/mn10300/kernel/
Dhead.S93 # invalidate and enable both of the caches
/linux-4.4.14/Documentation/filesystems/pohmelfs/
Ddesign_notes.txt8 metadata caches but is now evolving into a parallel distributed filesystem.
/linux-4.4.14/Documentation/devicetree/bindings/arm/msm/
Dqcom,idle-state.txt49 modes. In a hierarchical power domain SoC, this means L2 and other caches can
/linux-4.4.14/Documentation/filesystems/caching/
Dobject.txt41 of multiple caches:
84 multiple caches, but currently, non-index objects may not. Objects of any type
Dnetfs-api.txt184 in the hierarchy may be stored in multiple caches. This function does not
306 subtrees to be bound to particular caches, the second step is to look up cache
352 may be created in several different caches independently at different times.
463 Firstly, the netfs should ask FS-Cache to examine the caches and read the
831 copies of it will be removed from all active caches in which it is present.
Dfscache.txt132 caches.
Dcachefiles.txt108 Specify a tag to FS-Cache to use in distinguishing multiple caches.
Dbackend-api.txt5 The FS-Cache system provides an API by which actual caches can be supplied to
/linux-4.4.14/Documentation/cgroups/
Dmemory.txt41 - accounting anonymous pages, file caches, swap caches usage and limiting them.
237 caches are dropped. But as mentioned above, global LRU can do swapout memory
401 caches, RSS and Active pages/Inactive pages are shown.
470 Because rmdir() moves all pages to parent, some out-of-use page caches can be
789 pressure, the system might be making swap, paging out active file caches,
Dcpusets.txt316 then the kernel will spread some file system related slab caches,
333 or slab caches to ignore the task's NUMA mempolicy and be spread
355 PFA_SPREAD_SLAB, and appropriately marked slab caches will allocate
/linux-4.4.14/Documentation/networking/
Ddns_resolver.txt105 The kernel maintains an internal keyring in which it caches looked up keys.
/linux-4.4.14/fs/9p/
Dv9fs.c515 static struct kobj_attribute v9fs_attr_cache = __ATTR_RO(caches);
/linux-4.4.14/Documentation/scheduler/
Dsched-nice-design.txt44 this was long ago when hardware was weaker and caches were smaller, and
Dsched-design-CFS.txt124 caches but at the cost of interactivity. This is well suited for
/linux-4.4.14/Documentation/usb/
Ddma.txt67 semantics of dma-coherent memory require either bypassing CPU caches
/linux-4.4.14/arch/sh/mm/
DKconfig258 Selecting this option will configure the caches in write-through
/linux-4.4.14/fs/squashfs/
DKconfig203 By default SquashFS caches the last 3 fragments read from
/linux-4.4.14/Documentation/blockdev/
Dzram.txt10 use as swap disks, various caches under /var and maybe many more :)
/linux-4.4.14/Documentation/sysctl/
Dvm.txt189 Writing to this will cause the kernel to drop clean caches, as well as
206 This file is not a means to control the growth of the various kernel caches
767 to retain dentry and inode caches. When vfs_cache_pressure=0, the kernel will
/linux-4.4.14/fs/affs/
DChanges262 - Extension block caches are now allocated on
/linux-4.4.14/drivers/edac/
DKconfig346 Support for error detection and correction on the primary caches of
/linux-4.4.14/Documentation/RCU/
Drcu_dereference.txt60 interact directly with the hardware to flush instruction caches.
/linux-4.4.14/arch/arc/
DKconfig225 Linux only supports same line lengths for I and D caches.
/linux-4.4.14/Documentation/device-mapper/
Dcache.txt290 invalidation of larger caches. The cache must be in passthrough mode
/linux-4.4.14/Documentation/hid/
Dhid-transport.txt152 Normally, HID core caches any device state so this request is not necessary
/linux-4.4.14/Documentation/devicetree/bindings/arm/
Didle-states.txt106 the worst case since it depends on the CPU operating conditions, ie caches
/linux-4.4.14/Documentation/power/
Dswsusp.txt142 data and disk caches into "used memory" by saving them in
/linux-4.4.14/Documentation/development-process/
D4.Coding123 That, in turn, creates pressure on the processor's memory caches, which can
/linux-4.4.14/arch/mips/
DKconfig2115 # Support for a MIPS32 / MIPS64 style S-caches
2401 # caches such as R3000, SB1, R7000 or those that look like they're virtually
/linux-4.4.14/init/
DKconfig1752 Per cpu partial caches accellerate objects allocation and freeing
1754 in the latency of the free. On overflow these caches will be cleared
/linux-4.4.14/Documentation/filesystems/cifs/
DREADME450 behavior which caches reads (readahead) and writes