Searched refs:c13 (Results 1 - 21 of 21) sorted by relevance

/linux-4.4.14/arch/arm/include/asm/
H A Dtls.h13 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register variable
14 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register variable
15 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register variable
25 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register variable
26 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register variable
27 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register variable
81 asm("mcr p15, 0, %0, c13, c0, 3" set_tls()
104 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); get_tpuser()
115 asm("mcr p15, 0, %0, c13, c0, 2" set_tpuser()
H A Dpercpu.h27 asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); set_my_cpu_offset()
39 asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) __my_cpu_offset()
H A Darch_gicv3.h49 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
/linux-4.4.14/arch/arm/include/asm/hardware/
H A Dcp14.h78 #define RCP14_DBGBVR13() MRC14(0, c0, c13, 4)
94 #define RCP14_DBGBCR13() MRC14(0, c0, c13, 5)
110 #define RCP14_DBGWVR13() MRC14(0, c0, c13, 6)
126 #define RCP14_DBGWCR13() MRC14(0, c0, c13, 7)
143 #define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1)
183 #define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4)
199 #define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5)
215 #define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6)
231 #define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7)
247 #define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1)
294 #define RCP14_ETMVDCR1() MRC14(1, c0, c13, 0)
310 #define RCP14_ETMACVR13() MRC14(1, c0, c13, 1)
326 #define RCP14_ETMACTR13() MRC14(1, c0, c13, 2)
358 #define RCP14_ETMCNTVR1() MRC14(1, c0, c13, 5)
373 #define RCP14_ETMCIDCVR1() MRC14(1, c0, c13, 6)
389 #define RCP14_ETMEIBCR() MRC14(1, c0, c13, 7)
403 #define RCP14_ETMLSR() MRC14(1, c7, c13, 6)
416 #define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7)
431 #define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0)
447 #define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1)
463 #define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2)
495 #define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5)
510 #define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6)
525 #define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7)
/linux-4.4.14/arch/arm/mach-iop33x/
H A Dirq.c52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); intsize_write()
/linux-4.4.14/arch/arm/mm/
H A Dproc-v6.S109 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
114 mcr p15, 0, r1, c13, c0, 1 @ set context ID
142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
H A Dproc-v7-2level.S55 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
62 mcr p15, 0, r1, c13, c0, 1 @ set context ID
H A Dproc-sa1100.S179 mrc p15, 0, r5, c13, c0, 0 @ PID
195 mcr p15, 0, r5, c13, c0, 0 @ PID
H A Dcontext.c117 " mrc p15, 0, %0, c13, c0, 1\n" contextidr_notifier()
120 " mcr p15, 0, %0, c13, c0, 1\n" contextidr_notifier()
H A Dproc-v7.S99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
H A Dproc-feroceon.S343 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
344 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
523 mrc p15, 0, r4, c13, c0, 0 @ PID
535 mcr p15, 0, r4, c13, c0, 0 @ PID
H A Dproc-arm920.S393 mrc p15, 0, r4, c13, c0, 0 @ PID
405 mcr p15, 0, r4, c13, c0, 0 @ PID
H A Dproc-arm926.S408 mrc p15, 0, r4, c13, c0, 0 @ PID
420 mcr p15, 0, r4, c13, c0, 0 @ PID
H A Dproc-mohawk.S358 mrc p15, 0, r6, c13, c0, 0 @ PID
376 mcr p15, 0, r6, c13, c0, 0 @ PID
H A Dproc-xsc3.S421 mrc p15, 0, r6, c13, c0, 0 @ PID
439 mcr p15, 0, r6, c13, c0, 0 @ PID
H A Dproc-xscale.S536 mrc p15, 0, r6, c13, c0, 0 @ PID
552 mcr p15, 0, r6, c13, c0, 0 @ PID
/linux-4.4.14/arch/arm/kvm/
H A Dinterrupts_head.S277 mrc p15, 0, r2, c13, c0, 1 @ CID
278 mrc p15, 0, r3, c13, c0, 2 @ TID_URW
279 mrc p15, 0, r4, c13, c0, 3 @ TID_URO
280 mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV
360 mcr p15, 0, r2, c13, c0, 1 @ CID
361 mcr p15, 0, r3, c13, c0, 2 @ TID_URW
362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO
363 mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV
647 mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
H A Dinterrupts.S108 mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR
/linux-4.4.14/arch/arm64/kernel/
H A Dkuser32.S70 .inst 0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3
/linux-4.4.14/arch/arm/kernel/
H A Dperf_event_v7.c651 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); armv7pmu_read_counter()
654 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); armv7pmu_read_counter()
670 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); armv7pmu_write_counter()
673 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value)); armv7pmu_write_counter()
681 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); armv7_pmnc_write_evtsel()
749 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); armv7_pmnc_dump_regs()
755 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); armv7_pmnc_dump_regs()
758 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); armv7_pmnc_dump_regs()
H A Dentry-armv.S998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code

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