/linux-4.4.14/arch/arm/include/asm/ |
H A D | tls.h | 13 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register variable 14 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register variable 15 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register variable 25 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register variable 26 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register variable 27 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register variable 81 asm("mcr p15, 0, %0, c13, c0, 3" set_tls() 104 __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg)); get_tpuser() 115 asm("mcr p15, 0, %0, c13, c0, 2" set_tpuser()
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H A D | percpu.h | 27 asm volatile("mcr p15, 0, %0, c13, c0, 4" : : "r" (off) : "memory"); set_my_cpu_offset() 39 asm("mrc p15, 0, %0, c13, c0, 4" : "=r" (off) __my_cpu_offset()
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H A D | arch_gicv3.h | 49 #define __LR8(x) __ACCESS_CP15(c12, 4, c13, x)
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/linux-4.4.14/arch/arm/include/asm/hardware/ |
H A D | cp14.h | 78 #define RCP14_DBGBVR13() MRC14(0, c0, c13, 4) 94 #define RCP14_DBGBCR13() MRC14(0, c0, c13, 5) 110 #define RCP14_DBGWVR13() MRC14(0, c0, c13, 6) 126 #define RCP14_DBGWCR13() MRC14(0, c0, c13, 7) 143 #define RCP14_DBGBXVR13() MRC14(0, c1, c13, 1) 183 #define WCP14_DBGBVR13(val) MCR14(val, 0, c0, c13, 4) 199 #define WCP14_DBGBCR13(val) MCR14(val, 0, c0, c13, 5) 215 #define WCP14_DBGWVR13(val) MCR14(val, 0, c0, c13, 6) 231 #define WCP14_DBGWCR13(val) MCR14(val, 0, c0, c13, 7) 247 #define WCP14_DBGBXVR13(val) MCR14(val, 0, c1, c13, 1) 294 #define RCP14_ETMVDCR1() MRC14(1, c0, c13, 0) 310 #define RCP14_ETMACVR13() MRC14(1, c0, c13, 1) 326 #define RCP14_ETMACTR13() MRC14(1, c0, c13, 2) 358 #define RCP14_ETMCNTVR1() MRC14(1, c0, c13, 5) 373 #define RCP14_ETMCIDCVR1() MRC14(1, c0, c13, 6) 389 #define RCP14_ETMEIBCR() MRC14(1, c0, c13, 7) 403 #define RCP14_ETMLSR() MRC14(1, c7, c13, 6) 416 #define RCP14_ETMCIDR1() MRC14(1, c7, c13, 7) 431 #define WCP14_ETMVDCR1(val) MCR14(val, 1, c0, c13, 0) 447 #define WCP14_ETMACVR13(val) MCR14(val, 1, c0, c13, 1) 463 #define WCP14_ETMACTR13(val) MCR14(val, 1, c0, c13, 2) 495 #define WCP14_ETMCNTVR1(val) MCR14(val, 1, c0, c13, 5) 510 #define WCP14_ETMCIDCVR1(val) MCR14(val, 1, c0, c13, 6) 525 #define WCP14_ETMEIBCR(val) MCR14(val, 1, c0, c13, 7)
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/linux-4.4.14/arch/arm/mach-iop33x/ |
H A D | irq.c | 52 asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val)); intsize_write()
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/linux-4.4.14/arch/arm/mm/ |
H A D | proc-v6.S | 109 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 114 mcr p15, 0, r1, c13, c0, 1 @ set context ID 142 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 160 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 162 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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H A D | proc-v7-2level.S | 55 mrc p15, 0, r2, c13, c0, 1 @ read current context ID 62 mcr p15, 0, r1, c13, c0, 1 @ set context ID
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H A D | proc-sa1100.S | 179 mrc p15, 0, r5, c13, c0, 0 @ PID 195 mcr p15, 0, r5, c13, c0, 0 @ PID
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H A D | context.c | 117 " mrc p15, 0, %0, c13, c0, 1\n" contextidr_notifier() 120 " mcr p15, 0, %0, c13, c0, 1\n" contextidr_notifier()
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H A D | proc-v7.S | 99 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 100 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID 121 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID 123 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 124 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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H A D | proc-feroceon.S | 343 mcr p15, 5, r0, c15, c13, 0 @ D clean range start 344 mcr p15, 5, r1, c15, c13, 1 @ D clean range top 523 mrc p15, 0, r4, c13, c0, 0 @ PID 535 mcr p15, 0, r4, c13, c0, 0 @ PID
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H A D | proc-arm920.S | 393 mrc p15, 0, r4, c13, c0, 0 @ PID 405 mcr p15, 0, r4, c13, c0, 0 @ PID
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H A D | proc-arm926.S | 408 mrc p15, 0, r4, c13, c0, 0 @ PID 420 mcr p15, 0, r4, c13, c0, 0 @ PID
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H A D | proc-mohawk.S | 358 mrc p15, 0, r6, c13, c0, 0 @ PID 376 mcr p15, 0, r6, c13, c0, 0 @ PID
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H A D | proc-xsc3.S | 421 mrc p15, 0, r6, c13, c0, 0 @ PID 439 mcr p15, 0, r6, c13, c0, 0 @ PID
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H A D | proc-xscale.S | 536 mrc p15, 0, r6, c13, c0, 0 @ PID 552 mcr p15, 0, r6, c13, c0, 0 @ PID
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/linux-4.4.14/arch/arm/kvm/ |
H A D | interrupts_head.S | 277 mrc p15, 0, r2, c13, c0, 1 @ CID 278 mrc p15, 0, r3, c13, c0, 2 @ TID_URW 279 mrc p15, 0, r4, c13, c0, 3 @ TID_URO 280 mrc p15, 0, r5, c13, c0, 4 @ TID_PRIV 360 mcr p15, 0, r2, c13, c0, 1 @ CID 361 mcr p15, 0, r3, c13, c0, 2 @ TID_URW 362 mcr p15, 0, r4, c13, c0, 3 @ TID_URO 363 mcr p15, 0, r5, c13, c0, 4 @ TID_PRIV 647 mrc p15, 4, vcpu, c13, c0, 2 @ HTPIDR
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H A D | interrupts.S | 108 mcr p15, 4, vcpu, c13, c0, 2 @ HTPIDR
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/linux-4.4.14/arch/arm64/kernel/ |
H A D | kuser32.S | 70 .inst 0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3
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/linux-4.4.14/arch/arm/kernel/ |
H A D | perf_event_v7.c | 651 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); armv7pmu_read_counter() 654 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); armv7pmu_read_counter() 670 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value)); armv7pmu_write_counter() 673 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value)); armv7pmu_write_counter() 681 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); armv7_pmnc_write_evtsel() 749 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); armv7_pmnc_dump_regs() 755 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); armv7_pmnc_dump_regs() 758 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); armv7_pmnc_dump_regs()
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H A D | entry-armv.S | 998 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
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