Searched refs:bpp (Results 1 - 200 of 518) sorted by relevance

123

/linux-4.4.14/include/linux/platform_data/
H A Dshmob_drm.h31 SHMOB_DRM_IFACE_RGB8, /* 24bpp, 8:8:8 */
32 SHMOB_DRM_IFACE_RGB9, /* 18bpp, 9:9 */
33 SHMOB_DRM_IFACE_RGB12A, /* 24bpp, 12:12 */
34 SHMOB_DRM_IFACE_RGB12B, /* 12bpp */
35 SHMOB_DRM_IFACE_RGB16, /* 16bpp */
36 SHMOB_DRM_IFACE_RGB18, /* 18bpp */
37 SHMOB_DRM_IFACE_RGB24, /* 24bpp */
38 SHMOB_DRM_IFACE_YUV422, /* 16bpp */
39 SHMOB_DRM_IFACE_SYS8A, /* 24bpp, 8:8:8 */
40 SHMOB_DRM_IFACE_SYS8B, /* 18bpp, 8:8:2 */
41 SHMOB_DRM_IFACE_SYS8C, /* 18bpp, 2:8:8 */
42 SHMOB_DRM_IFACE_SYS8D, /* 16bpp, 8:8 */
43 SHMOB_DRM_IFACE_SYS9, /* 18bpp, 9:9 */
44 SHMOB_DRM_IFACE_SYS12, /* 24bpp, 12:12 */
45 SHMOB_DRM_IFACE_SYS16A, /* 16bpp */
46 SHMOB_DRM_IFACE_SYS16B, /* 18bpp, 16:2 */
47 SHMOB_DRM_IFACE_SYS16C, /* 18bpp, 2:16 */
48 SHMOB_DRM_IFACE_SYS18, /* 18bpp */
49 SHMOB_DRM_IFACE_SYS24, /* 24bpp */
H A Dvideo-imxfb.h57 unsigned char bpp; member in struct:imx_fb_videomode
H A Dvideo-nuc900fb.h53 unsigned short bpp; member in struct:nuc900fb_display
/linux-4.4.14/drivers/video/fbdev/
H A Dc2p_iplan2.c48 static inline void store_iplan2(void *dst, u32 bpp, u32 d[4]) store_iplan2() argument
52 for (i = 0; i < bpp/2; i++, dst += 4) store_iplan2()
61 static inline void store_iplan2_masked(void *dst, u32 bpp, u32 d[4], u32 mask) store_iplan2_masked() argument
65 for (i = 0; i < bpp/2; i++, dst += 4) store_iplan2_masked()
82 * @bpp: Bits per pixel of the planar frame buffer (2, 4, or 8)
86 u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp) c2p_iplan2()
96 dst += dy*dst_nextline+(dx & ~15)*bpp; c2p_iplan2()
113 store_iplan2_masked(p, bpp, d.words, first); c2p_iplan2()
114 p += bpp*2; c2p_iplan2()
125 store_iplan2_masked(p, bpp, d.words, first); c2p_iplan2()
126 p += bpp*2; c2p_iplan2()
134 store_iplan2(p, bpp, d.words); c2p_iplan2()
135 p += bpp*2; c2p_iplan2()
144 store_iplan2_masked(p, bpp, d.words, last); c2p_iplan2()
85 c2p_iplan2(void *dst, const void *src, u32 dx, u32 dy, u32 width, u32 height, u32 dst_nextline, u32 src_nextline, u32 bpp) c2p_iplan2() argument
H A Dc2p_planar.c48 static inline void store_planar(void *dst, u32 dst_inc, u32 bpp, u32 d[8]) store_planar() argument
52 for (i = 0; i < bpp; i++, dst += dst_inc) store_planar()
61 static inline void store_planar_masked(void *dst, u32 dst_inc, u32 bpp, store_planar_masked() argument
66 for (i = 0; i < bpp; i++, dst += dst_inc) store_planar_masked()
83 * @bpp: Bits per pixel of the planar frame buffer (1-8)
88 u32 src_nextline, u32 bpp) c2p_planar()
113 store_planar_masked(p, dst_nextplane, bpp, d.words, c2p_planar()
126 store_planar_masked(p, dst_nextplane, bpp, c2p_planar()
136 store_planar(p, dst_nextplane, bpp, d.words); c2p_planar()
146 store_planar_masked(p, dst_nextplane, bpp, c2p_planar()
86 c2p_planar(void *dst, const void *src, u32 dx, u32 dy, u32 width, u32 height, u32 dst_nextline, u32 dst_nextplane, u32 src_nextline, u32 bpp) c2p_planar() argument
H A Damba-clcd-versatile.c28 .bpp = 16,
52 .bpp = 16,
77 .bpp = 16,
101 .bpp = 16,
126 .bpp = 16,
H A Dsh7760fb.c125 u16 lddfr, int *bpp, int *gray) sh7760fb_get_color_info()
160 if (bpp) sh7760fb_get_color_info()
161 *bpp = lbpp; sh7760fb_get_color_info()
173 int ret, bpp; sh7760fb_check_var() local
176 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL); sh7760fb_check_var()
180 var->bits_per_pixel = bpp; sh7760fb_check_var()
207 int ret, bpp, gray; sh7760fb_set_par() local
228 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, &gray); sh7760fb_set_par()
233 vdln, bpp, gray ? "grayscale" : "color", sh7760fb_set_par()
273 stride *= (bpp + 7) >> 3; sh7760fb_set_par()
275 if (bpp == 1) sh7760fb_set_par()
277 else if (bpp == 2) sh7760fb_set_par()
279 else if (bpp == 4) sh7760fb_set_par()
281 /* 6 bpp == 8 bpp */ sh7760fb_set_par()
381 int ret, bpp; sh7760fb_alloc_mem() local
387 ret = sh7760fb_get_color_info(info->dev, par->pd->lddfr, &bpp, NULL); sh7760fb_alloc_mem()
393 /* min VRAM: xres_min = 16, yres_min = 1, bpp = 1: 2byte -> 1 page sh7760fb_alloc_mem()
394 max VRAM: xres_max = 1024, yres_max = 1024, bpp = 16: 2MB */ sh7760fb_alloc_mem()
398 if (bpp == 1) sh7760fb_alloc_mem()
400 else if (bpp == 2) sh7760fb_alloc_mem()
402 else if (bpp == 4) sh7760fb_alloc_mem()
404 } else if (bpp > 8) sh7760fb_alloc_mem()
124 sh7760fb_get_color_info(struct device *dev, u16 lddfr, int *bpp, int *gray) sh7760fb_get_color_info() argument
H A Dtridentfb.c63 static int bpp = 8; variable
81 module_param(bpp, int, 0);
304 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp) blade_init_accel() argument
307 int tmp = bpp == 24 ? 2 : (bpp >> 4); blade_init_accel()
378 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp) xp_init_accel() argument
380 unsigned char x = bpp == 24 ? 3 : (bpp >> 4); xp_init_accel()
381 int v1 = pitch << (bpp == 24 ? 20 : (18 + x)); xp_init_accel()
383 switch (pitch << (bpp >> 3)) { xp_init_accel()
476 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp) image_init_accel() argument
478 int tmp = bpp == 24 ? 2: (bpp >> 4); image_init_accel()
542 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp) tgui_init_accel() argument
544 unsigned char x = bpp == 24 ? 3 : (bpp >> 4); tgui_init_accel()
550 switch ((pitch * bpp) / 8) { tgui_init_accel()
996 int bpp = var->bits_per_pixel; tridentfb_check_var() local
1002 if (bpp == 24) tridentfb_check_var()
1003 bpp = var->bits_per_pixel = 32; tridentfb_check_var()
1004 if (bpp != 8 && bpp != 16 && bpp != 32) tridentfb_check_var()
1006 if (par->chip_id == TGUI9440 && bpp == 32) tridentfb_check_var()
1022 line_length = var->xres_virtual * bpp / 8; tridentfb_check_var()
1028 var->xres_virtual = 512 * 8 / bpp; tridentfb_check_var()
1030 var->xres_virtual = 1024 * 8 / bpp; tridentfb_check_var()
1032 var->xres_virtual = 2048 * 8 / bpp; tridentfb_check_var()
1034 var->xres_virtual = 4096 * 8 / bpp; tridentfb_check_var()
1036 var->xres_virtual = 8192 * 8 / bpp; tridentfb_check_var()
1040 line_length = var->xres_virtual * bpp / 8; tridentfb_check_var()
1050 switch (bpp) { tridentfb_check_var()
1082 ramdac = (bpp >= 16) ? 45000 : 90000; tridentfb_check_var()
1096 /* The clock is doubled for 32 bpp */ tridentfb_check_var()
1097 if (bpp == 32) tridentfb_check_var()
1141 int bpp = var->bits_per_pixel; tridentfb_set_par() local
1264 switch (bpp) { tridentfb_set_par()
1305 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */ tridentfb_set_par()
1307 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) { tridentfb_set_par()
1328 switch (bpp) { tridentfb_set_par()
1351 info->fix.line_length = info->var.xres_virtual * bpp / 8; tridentfb_set_par()
1355 par->init_accel(par, info->var.xres_virtual, bpp); tridentfb_set_par()
1357 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; tridentfb_set_par()
1358 info->cmap.len = (bpp == 8) ? 256 : 16; tridentfb_set_par()
1368 int bpp = info->var.bits_per_pixel; tridentfb_setcolreg() local
1374 if (bpp == 8) { tridentfb_setcolreg()
1383 if (bpp == 16) { /* RGB 565 */ tridentfb_setcolreg()
1390 } else if (bpp == 32) /* ARGB 8888 */ tridentfb_setcolreg()
1777 * video=trident:800x600,bpp=16,noaccel
1794 else if (!strncmp(opt, "bpp=", 4)) tridentfb_setup()
1795 bpp = simple_strtoul(opt + 4, NULL, 0); tridentfb_setup()
H A Dsbuslib.h15 struct device_node *dp, int bpp);
H A Dpxafb.c237 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */ var_to_depth()
247 int bpp = -EINVAL; pxafb_var_to_bpp() local
250 case 1: bpp = 0; break; pxafb_var_to_bpp()
251 case 2: bpp = 1; break; pxafb_var_to_bpp()
252 case 4: bpp = 2; break; pxafb_var_to_bpp()
253 case 8: bpp = 3; break; pxafb_var_to_bpp()
254 case 16: bpp = 4; break; pxafb_var_to_bpp()
257 case 18: bpp = 6; break; /* 18-bits/pixel packed */ pxafb_var_to_bpp()
258 case 19: bpp = 8; break; /* 19-bits/pixel packed */ pxafb_var_to_bpp()
259 case 24: bpp = 9; break; pxafb_var_to_bpp()
264 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */ pxafb_var_to_bpp()
265 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */ pxafb_var_to_bpp()
266 case 25: bpp = 10; break; pxafb_var_to_bpp()
270 return bpp; pxafb_var_to_bpp()
286 int bpp = pxafb_var_to_bpp(var); pxafb_var_to_lccr3() local
289 if (bpp < 0) pxafb_var_to_lccr3()
292 lccr3 = LCCR3_BPP(bpp); pxafb_var_to_lccr3()
377 modelist[i].bpp >= var->bits_per_pixel) { pxafb_getmode()
392 var->bits_per_pixel = mode->bpp; pxafb_setmode()
564 * 16 bpp mode does not really use the palette, so this will not
765 int xpos, ypos, pfor, bpp; overlayfb_check_var() local
771 bpp = pxafb_var_to_bpp(var); overlayfb_check_var()
772 if (bpp < 0) overlayfb_check_var()
779 /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */ overlayfb_check_var()
782 bpp = pxafb_var_to_bpp(var); overlayfb_check_var()
783 if (bpp < 0) overlayfb_check_var()
788 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; overlayfb_check_var()
789 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break; overlayfb_check_var()
790 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break; overlayfb_check_var()
791 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break; overlayfb_check_var()
797 if ((xpos * bpp) % 32) overlayfb_check_var()
801 var->xres = roundup(var->xres * bpp, 32) / bpp; overlayfb_check_var()
816 int size, bpp = 0; overlayfb_check_video_memory() local
819 case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break; overlayfb_check_video_memory()
820 case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break; overlayfb_check_video_memory()
821 case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break; overlayfb_check_video_memory()
822 case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break; overlayfb_check_video_memory()
823 case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break; overlayfb_check_video_memory()
826 ofb->fb.fix.line_length = var->xres_virtual * bpp / 8; overlayfb_check_video_memory()
841 int xpos, ypos, pfor, bpp, ret; overlayfb_set_par() local
847 bpp = pxafb_var_to_bpp(var); overlayfb_set_par()
853 OVLxC1_BPP(bpp); overlayfb_set_par()
910 * anyway, it's useless to use 16bpp main plane and 24bpp overlay pxafb_overlay_map_video_memory()
1109 int nbytes, dma, pal, bpp = var->bits_per_pixel; setup_base_frame() local
1113 pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0); setup_base_frame()
1782 m->xres * m->yres * m->bpp / 8); pxafb_decode_mach_info()
1862 unsigned int xres = 0, yres = 0, bpp = 0; parse_opt_mode() local
1870 bpp = simple_strtoul(&name[i+1], NULL, 0); parse_opt_mode()
1898 switch (bpp) { parse_opt_mode()
1904 inf->modes[0].bpp = bpp; parse_opt_mode()
1905 dev_info(dev, "overriding bit depth: %d\n", bpp); parse_opt_mode()
1908 dev_err(dev, "Depth %d is not valid\n", bpp); parse_opt_mode()
2119 inf->modes->bpp); pxafb_probe()
2122 inf->modes->bpp == 0) { pxafb_probe()
H A Ds1d13xxxfb.c210 dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel); s1d13xxxfb_set_par()
237 dbg("bpp not supported!\n"); s1d13xxxfb_set_par()
451 u16 bpp; s1d13xxxfb_bitblt_copyarea() local
456 bpp = (info->var.bits_per_pixel >> 3); s1d13xxxfb_bitblt_copyarea()
457 stride = bpp * info->var.xres; s1d13xxxfb_bitblt_copyarea()
461 dst = (((dy + height - 1) * stride) + (bpp * (dx + width - 1))); s1d13xxxfb_bitblt_copyarea()
462 src = (((sy + height - 1) * stride) + (bpp * (sx + width - 1))); s1d13xxxfb_bitblt_copyarea()
465 } else { /* (y * xres) + (bpp * x) */ s1d13xxxfb_bitblt_copyarea()
466 dst = (dy * stride) + (bpp * dx); s1d13xxxfb_bitblt_copyarea()
467 src = (sy * stride) + (bpp * sx); s1d13xxxfb_bitblt_copyarea()
499 /* setup the bpp 1 = 16bpp, 0 = 8bpp*/ s1d13xxxfb_bitblt_copyarea()
500 s1d13xxxfb_writereg(info->par, S1DREG_BBLT_CTL1, (bpp >> 1)); s1d13xxxfb_bitblt_copyarea()
510 dbg_blit("(copyarea) bpp=%d=0x0%d, mem_offset1=%d, mem_offset2=%d\n", bpp, (bpp >> 1), s1d13xxxfb_bitblt_copyarea()
538 u16 bpp = (info->var.bits_per_pixel >> 3); s1d13xxxfb_bitblt_solidfill() local
544 screen_stride = (bpp * info->var.xres); s1d13xxxfb_bitblt_solidfill()
547 dest = ((rect->dy * screen_stride) + (bpp * rect->dx)); s1d13xxxfb_bitblt_solidfill()
554 dbg_blit("(solidfill) : xres=%d, yres=%d, bpp=%d\n", s1d13xxxfb_bitblt_solidfill()
592 /* set bits per pixel (1 = 16bpp, 0 = 8bpp) */ s1d13xxxfb_bitblt_solidfill()
653 int bpp, lcd_bpp; s1d13xxxfb_fetch_hw_state() local
672 bpp = display & 0x07; s1d13xxxfb_fetch_hw_state()
674 switch (bpp) { s1d13xxxfb_fetch_hw_state()
675 case 2: /* 4 bpp */ s1d13xxxfb_fetch_hw_state()
676 case 3: /* 8 bpp */ s1d13xxxfb_fetch_hw_state()
681 case 5: /* 16 bpp */ s1d13xxxfb_fetch_hw_state()
685 dbg("bpp: %i\n", bpp); s1d13xxxfb_fetch_hw_state()
726 dbg(PFX "bpp=%d, lcd_bpp=%d, " s1d13xxxfb_fetch_hw_state()
H A Dau1100fb.h78 u32 bpp; /* Maximum depth supported */ member in struct:au1100fb_panel
276 .bpp = 16,
289 .bpp = 16,
300 .bpp = 16,
327 .bpp = 4,
349 .bpp = 16,
361 .bpp = 16,
H A Dbfin_adv7393fb.h68 u16 bpp; member in struct:adv7393fb_modes
170 .bpp = 16,
186 .bpp = 16,
202 .bpp = 16,
218 .bpp = 16,
234 .bpp = 16,
250 .bpp = 16,
H A Dsa1100fb.h76 #define SA1100_PALETTE_MODE_VAL(bpp) (((bpp) & 0x018) << 9)
H A Datafb.c149 short bpp; member in struct:atafb_par::__anon11092::falcon_hw
620 int bpp = var->bits_per_pixel; tt_decode_var() local
625 if (bpp > 1 || xres > sttt_xres * 2 || yres > tt_yres * 2) tt_decode_var()
630 bpp = 1; tt_decode_var()
632 if (bpp > 8 || xres > sttt_xres || yres > tt_yres) tt_decode_var()
634 if (bpp > 4) { tt_decode_var()
640 bpp = 8; tt_decode_var()
641 } else if (bpp > 2) { tt_decode_var()
648 bpp = 4; tt_decode_var()
653 bpp = 4; tt_decode_var()
655 } else if (bpp > 1) { tt_decode_var()
661 bpp = 2; tt_decode_var()
668 bpp = 1; tt_decode_var()
679 linelen = xres * bpp / 8; tt_decode_var()
920 int bpp = var->bits_per_pixel; falcon_decode_var() local
961 if (!xres || !yres || !bpp) falcon_decode_var()
964 if (mon_type == F_MON_SM && bpp != 1) falcon_decode_var()
967 if (bpp <= 1) { falcon_decode_var()
968 bpp = 1; falcon_decode_var()
971 } else if (bpp <= 2) { falcon_decode_var()
972 bpp = 2; falcon_decode_var()
975 } else if (bpp <= 4) { falcon_decode_var()
976 bpp = 4; falcon_decode_var()
979 } else if (bpp <= 8) { falcon_decode_var()
980 bpp = 8; falcon_decode_var()
982 } else if (bpp <= 16) { falcon_decode_var()
983 bpp = 16; /* packed pixel mode */ falcon_decode_var()
987 par->hw.falcon.bpp = bpp; falcon_decode_var()
993 if (bpp > myvar->bits_per_pixel || falcon_decode_var()
1004 else if (xres <= 640 && bpp != 16) falcon_decode_var()
1014 par->hw.falcon.ste_mode = bpp == 2; falcon_decode_var()
1015 par->hw.falcon.mono = bpp == 1; falcon_decode_var()
1027 else if (bpp == 1) falcon_decode_var()
1038 else if (bpp == 1) falcon_decode_var()
1052 par->hw.falcon.line_width = bpp * xres / 16; falcon_decode_var()
1053 par->hw.falcon.line_offset = bpp * (xres_virtual - xres) / 16; falcon_decode_var()
1106 if (bpp == 16) falcon_decode_var()
1185 if (pclock->f / plen / 8 * bpp > 32000000L) falcon_decode_var()
1230 * (this must be a multiple of plen*128/bpp, on VGA pixels falcon_decode_var()
1254 align = 128 / bpp; falcon_decode_var()
1255 hde_off = ((128 / bpp + 2) * plen); falcon_decode_var()
1257 hdb_off = (64 + base_off + (128 / bpp + 2) * plen) + prescale; falcon_decode_var()
1259 hdb_off = (base_off + (128 / bpp + 18) * plen) + prescale; falcon_decode_var()
1377 linelen = xres_virtual * bpp / 8; falcon_decode_var()
1434 * to get bpp, we must examine f_shift and st_shift. falcon_encode_var()
1682 int bpp = info->var.bits_per_pixel; falcon_pan_display() local
1684 if (bpp == 1) falcon_pan_display()
1686 if (bpp != 16) falcon_pan_display()
1692 par->hw.falcon.line_offset = bpp * falcon_pan_display()
1695 par->hw.falcon.line_offset -= bpp; falcon_pan_display()
1699 (var->yoffset * info->var.xres_virtual + xoffset) * bpp / 8; falcon_pan_display()
1847 int bpp = var->bits_per_pixel; stste_decode_var() local
1852 if (bpp > 1 || xres > sttt_xres || yres > st_yres) stste_decode_var()
1857 bpp = 1; stste_decode_var()
1859 if (bpp > 4 || xres > sttt_xres || yres > st_yres) stste_decode_var()
1861 if (bpp > 2) { stste_decode_var()
1867 bpp = 4; stste_decode_var()
1868 } else if (bpp > 1) { stste_decode_var()
1874 bpp = 2; stste_decode_var()
1886 linelen = xres * bpp / 8; stste_decode_var()
H A Di740fb.c208 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp) i740_calc_fifo() argument
220 switch (bpp) { i740_calc_fifo()
404 u32 bpp, base, dacspeed24, mem; i740fb_decode_var() local
410 dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n", i740fb_decode_var()
422 bpp = var->bits_per_pixel; i740fb_decode_var()
423 switch (bpp) { i740fb_decode_var()
425 bpp = 8; i740fb_decode_var()
427 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n", i740fb_decode_var()
433 bpp = 15; i740fb_decode_var()
436 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n", i740fb_decode_var()
442 bpp = 24; i740fb_decode_var()
445 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n", i740fb_decode_var()
451 bpp = 32; i740fb_decode_var()
453 dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n", i740fb_decode_var()
488 mem = vxres * vyres * ((bpp + 1) / 8); i740fb_decode_var()
583 switch (bpp) { i740fb_decode_var()
642 /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */ i740fb_decode_var()
653 i740_calc_fifo(par, 1000000 / var->pixclock, bpp); i740fb_decode_var()
866 dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n", i740fb_setcolreg()
916 * address register in 24bpp mode, so... i740fb_pan_display()
H A Dpm3fb.c182 static inline int pm3fb_shift_bpp(unsigned bpp, int v) pm3fb_shift_bpp() argument
184 switch (bpp) { pm3fb_shift_bpp()
192 DPRINTK("Unsupported depth %u\n", bpp); pm3fb_shift_bpp()
620 /* Too large of a cursor or wrong bpp :-( */ pm3fb_cursor()
731 const unsigned bpp = info->var.bits_per_pixel; pm3fb_write_mode() local
740 pm3fb_shift_bpp(bpp, htotal - 1)); pm3fb_write_mode()
742 pm3fb_shift_bpp(bpp, hsend)); pm3fb_write_mode()
744 pm3fb_shift_bpp(bpp, hsstart)); pm3fb_write_mode()
746 pm3fb_shift_bpp(bpp, hbend)); pm3fb_write_mode()
748 pm3fb_shift_bpp(bpp, hbend)); pm3fb_write_mode()
750 pm3fb_shift_bpp(bpp, width)); pm3fb_write_mode()
756 switch (bpp) { pm3fb_write_mode()
797 DPRINTK("Unsupported depth %d\n", bpp); pm3fb_write_mode()
914 unsigned bpp = var->red.length + var->green.length pm3fb_check_var() local
917 if (bpp != var->bits_per_pixel) { pm3fb_check_var()
1017 const unsigned bpp = info->var.bits_per_pixel; pm3fb_set_par() local
1019 par->base = pm3fb_shift_bpp(bpp, (info->var.yoffset * xres) pm3fb_set_par()
1041 switch (bpp) { pm3fb_set_par()
1057 (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; pm3fb_set_par()
1058 info->fix.line_length = ((info->var.xres_virtual + 7) >> 3) * bpp; pm3fb_set_par()
H A Dda8xx-fb.c480 if (cfg->bpp == 12 && cfg->stn_565_mode) lcd_cfg_display()
524 u32 bpp, u32 raster_order) lcd_cfg_frame_buffer()
528 if (bpp > 16 && lcd_revision == LCD_VERSION_1) lcd_cfg_frame_buffer()
577 switch (bpp) { lcd_cfg_frame_buffer()
783 u32 bpp; lcd_init() local
815 bpp = cfg->bpp; lcd_init()
817 if (bpp == 12) lcd_init()
818 bpp = 16; lcd_init()
820 (unsigned int)panel->yres, bpp, lcd_init()
955 int bpp = var->bits_per_pixel >> 3; fb_check_var() local
956 unsigned long line_size = var->xres_virtual * bpp; fb_check_var()
1277 par->cfg.bpp = info->var.bits_per_pixel; da8xxfb_set_par()
1279 info->fix.visual = (par->cfg.bpp <= 8) ? da8xxfb_set_par()
1281 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8; da8xxfb_set_par()
1423 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp; fb_probe()
1424 ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE); fb_probe()
1442 da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8; fb_probe()
1467 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp; fb_probe()
523 lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height, u32 bpp, u32 raster_order) lcd_cfg_frame_buffer() argument
H A Damba-clcd.c234 * >= 16bpp displays have separate colour component bitfields clcdfb_set_bitfields()
490 fb->fb.var.bits_per_pixel = fb->panel->bpp; clcdfb_register()
654 unsigned int bpp; clcdfb_of_init_display() local
680 bpp = max_bandwidth / (1000 / 8) clcdfb_of_init_display()
682 bpp = rounddown_pow_of_two(bpp); clcdfb_of_init_display()
683 if (bpp > 32) clcdfb_of_init_display()
684 bpp = 32; clcdfb_of_init_display()
686 bpp = 32; clcdfb_of_init_display()
687 fb->panel->bpp = bpp; clcdfb_of_init_display()
763 fb->panel->bpp / 8; clcdfb_of_dma_setup()
H A Dsunxvr500.c85 #define RAMDAC_VID_32FB_0 0x00000078UL /* PCI base 32bpp FB buffer 0 */
86 #define RAMDAC_VID_32FB_1 0x0000007cUL /* PCI base 32bpp FB buffer 1 */
87 #define RAMDAC_VID_8FB_0 0x00000080UL /* PCI base 8bpp FB buffer 0 */
88 #define RAMDAC_VID_8FB_1 0x00000084UL /* PCI base 8bpp FB buffer 1 */
143 * XXX two 8bpp areas of the framebuffer work. I imagine there is
145 * XXX the ramdac which of the two 8bpp framebuffer regions to take
H A Dp9100.c66 /* 3 bits: 2=8bpp 3=16bpp 5=32bpp 7=24bpp */
H A Dstifb.c42 * - 1bpp mode is completely untested
50 * #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
1126 int bpp, xres, yres; stifb_init_fb() local
1175 /* default to 8 bpp on most graphic chips */ stifb_init_fb()
1176 bpp = 8; stifb_init_fb()
1210 bpp = 32; stifb_init_fb()
1223 bpp = bpp_pref; stifb_init_fb()
1225 bpp = 32; stifb_init_fb()
1227 bpp = 8; stifb_init_fb()
1238 "- now trying 1bpp mode instead\n", stifb_init_fb()
1240 bpp = 1; /* default to 1 bpp */ stifb_init_fb()
1256 fix->line_length = (fb->sti->glob_cfg->total_x * bpp) / 8; stifb_init_fb()
1266 switch (bpp) { stifb_init_fb()
1292 var->bits_per_pixel = bpp; stifb_init_fb()
1436 if (strncmp(options, "bpp", 3) == 0) { stifb_setup()
H A Dmacfb.c201 unsigned int bpp = info->var.bits_per_pixel; v8_brazil_setpalette() local
204 if (bpp > 8) v8_brazil_setpalette()
211 * In 8bpp, all regnos are valid. v8_brazil_setpalette()
212 * In 4bpp, the regnos are 0x0f, 0x1f, 0x2f, etc, etc v8_brazil_setpalette()
213 * In 2bpp, the regnos are 0x3f, 0x7f, 0xbf, 0xff v8_brazil_setpalette()
215 regno = (regno << (8 - bpp)) | (0xFF >> bpp); v8_brazil_setpalette()
296 unsigned int bpp = info->var.bits_per_pixel; toby_setpalette() local
302 regno = (regno << (8 - bpp)) | (0xFF >> bpp); toby_setpalette()
H A Dtdfxfb.c25 * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
94 /* "640x480, 8 bpp @ 60 Hz */
277 * Set the color of a palette entry in 8bpp mode
847 u32 bpp = info->var.bits_per_pixel; tdfxfb_fillrect() local
849 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); tdfxfb_fillrect()
867 dstbase += dx * bpp >> 3; tdfxfb_fillrect()
891 u32 bpp = info->var.bits_per_pixel; tdfxfb_copyarea() local
894 u32 fmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); tdfxfb_copyarea()
905 srcbase += sx * bpp >> 3; tdfxfb_copyarea()
915 dstbase += dx * bpp >> 3; tdfxfb_copyarea()
950 u32 bpp = info->var.bits_per_pixel; tdfxfb_imageblit() local
951 u32 dstfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13); tdfxfb_imageblit()
961 srcfmt = stride | ((bpp + ((bpp == 8) ? 0 : 8)) << 13) | tdfxfb_imageblit()
993 dstbase += dx * bpp >> 3; tdfxfb_imageblit()
1047 /* Too large of a cursor or wrong bpp :-( */ tdfxfb_cursor()
H A Damifb.c722 u_short bpp; /* vmode */ member in struct:amifb_par
1155 par->bpp = var->bits_per_pixel; ami_decode_var()
1157 if (par->bpp < 1) ami_decode_var()
1158 par->bpp = 1; ami_decode_var()
1159 if (par->bpp > maxdepth[clk_shift]) { ami_decode_var()
1161 par->bpp = maxdepth[clk_shift]; ami_decode_var()
1163 DPRINTK("invalid bpp\n"); ami_decode_var()
1168 if (par->bpp < 6) ami_decode_var()
1169 par->bpp = 6; ami_decode_var()
1170 if (par->bpp != 6) { ami_decode_var()
1171 if (par->bpp < 8) ami_decode_var()
1172 par->bpp = 8; ami_decode_var()
1173 if (par->bpp != 8 || !IS_AGA) { ami_decode_var()
1174 DPRINTK("invalid bpp for ham mode\n"); ami_decode_var()
1431 if (par->htotal - fsize - 64 < par->bpp * 64) ami_decode_var()
1440 par->next_line = par->bpp * par->next_plane; ami_decode_var()
1448 if (par->next_plane * par->bpp > info->fix.smem_len) { ami_decode_var()
1461 if (par->bpp == 8) ami_decode_var()
1464 par->bplcon0 |= par->bpp << 12; ami_decode_var()
1528 var->bits_per_pixel = par->bpp; ami_encode_var()
1533 var->red.length = par->bpp; ami_encode_var()
2167 for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) { ami_rebuild_copper()
2185 for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) { ami_rebuild_copper()
2201 for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) { ami_rebuild_copper()
2224 for (i = 0; i < (short)par->bpp; i++, p += par->next_plane) { ami_rebuild_copper()
2412 if (par->bpp == 1) { amifb_set_par()
3135 static inline void fill_one_line(int bpp, unsigned long next_plane, fill_one_line() argument
3143 if (!--bpp) fill_one_line()
3150 static inline void xor_one_line(int bpp, unsigned long next_plane, xor_one_line() argument
3158 if (!--bpp) xor_one_line()
3209 static inline void copy_one_line(int bpp, unsigned long next_plane, copy_one_line() argument
3219 if (!--bpp) copy_one_line()
3226 static inline void copy_one_line_rev(int bpp, unsigned long next_plane, copy_one_line_rev() argument
3236 if (!--bpp) copy_one_line_rev()
3308 static inline void expand_one_line(int bpp, unsigned long next_plane, expand_one_line() argument
3329 if (!--bpp) expand_one_line()
H A Dau1200fb.c310 /* Need VGA 640 @ 24bpp, @ 32bpp */
311 /* Need VGA 800 @ 24bpp, @ 32bpp */
312 /* Need VGA 1024 @ 24bpp, @ 32bpp */
1092 /* 16bpp True color. au1200fb_fb_check_var()
1105 /* 32bpp True color. au1200fb_fb_check_var()
1291 unsigned int val, bpp; set_window() local
1345 bpp = winbpp(val) / 8; set_window()
1347 val |= (((pdata->xsize * bpp) << 8) & LCD_WINCTRL2_BX); set_window()
1520 int bpp; au1200fb_init_fbinfo() local
1524 bpp = winbpp(win->w[fbdev->plane].mode_winctrl1); au1200fb_init_fbinfo()
1541 bpp)) { au1200fb_init_fbinfo()
1651 int bpp, plane, ret, irq; au1200fb_drv_probe() local
1675 bpp = winbpp(win->w[plane].mode_winctrl1); au1200fb_drv_probe()
1694 fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8; au1200fb_drv_probe()
H A Ds3c2410fb.c139 var->bits_per_pixel == default_display->bpp) s3c2410fb_check_var()
146 var->bits_per_pixel == mach_info->displays[i].bpp) { s3c2410fb_check_var()
152 dprintk("wrong resolution or depth %dx%d at %d bpp\n", s3c2410fb_check_var()
190 /* 8 bpp 332 */ s3c2410fb_check_var()
205 /* 12 bpp 444 */ s3c2410fb_check_var()
217 /* 16 bpp, 565 format */ s3c2410fb_check_var()
225 /* 16 bpp, 5551 format */ s3c2410fb_check_var()
235 /* 24 bpp 888 and 8 dummy */ s3c2410fb_check_var()
285 dev_err(fbi->dev, "invalid bpp %d\n", s3c2410fb_calculate_stn_lcd_regs()
346 dev_err(fbi->dev, "invalid bpp %d\n", s3c2410fb_calculate_tft_lcd_regs()
385 dprintk("%s: var->bpp = %d\n", __func__, var->bits_per_pixel); s3c2410fb_activate_var()
947 smem_len *= mach_info->displays[i].bpp; s3c24xxfb_probe()
965 fbinfo->var.bits_per_pixel = display->bpp; s3c24xxfb_probe()
H A Dvt8623fb.c379 u32 bpp = info->var.bits_per_pixel; vt8623fb_set_par() local
381 if (bpp != 0) { vt8623fb_set_par()
383 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; vt8623fb_set_par()
388 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ vt8623fb_set_par()
389 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); vt8623fb_set_par()
392 offset_value = (info->var.xres_virtual * bpp) / 64; vt8623fb_set_par()
393 fetch_value = ((info->var.xres * bpp) / 128) + 4; vt8623fb_set_par()
395 if (bpp == 4) vt8623fb_set_par()
H A Ds3c-fb.c227 * @bpp: The bit depth.
229 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp) s3c_fb_validate_win_bpp() argument
231 return win->variant.valid_bpp & VALID_BPP(bpp); s3c_fb_validate_win_bpp()
254 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n", s3c_fb_check_var()
304 /* 16 bpp, 565 format */ s3c_fb_check_var()
320 /* our 24bpp is unpacked, so 32bpp */ s3c_fb_check_var()
331 dev_err(sfb->dev, "invalid bpp\n"); s3c_fb_check_var()
372 * @bpp: The number of bits per pixel
378 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix) s3c_fb_align_word() argument
382 if (bpp > 16) s3c_fb_align_word()
385 pix_per_word = (8 * 32) / bpp; s3c_fb_align_word()
879 /* X offset depends on the current bpp */ s3c_fb_pan_display()
894 dev_err(sfb->dev, "invalid bpp\n"); s3c_fb_pan_display()
1232 /* Set 8bpp or 8bpp and 1bit alpha */ s3c_fb_probe_win()
H A Dwm8505fb.c272 u32 bpp; wm8505fb_probe() local
319 ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp); wm8505fb_probe()
332 fb_mem_len = mode.xres * mode.yres * 2 * (bpp / 8); wm8505fb_probe()
342 fbi->fb.var.bits_per_pixel = bpp; wm8505fb_probe()
H A Dimsttfb.c123 PIXFMT = 0x0a, /* () Pixel Format [bpp >> 3 + 2] */
564 set_imstt_regvals_ibm (struct imstt_par *par, u_int bpp) set_imstt_regvals_ibm() argument
567 __u8 pformat = (bpp >> 3) + 2; set_imstt_regvals_ibm()
584 set_imstt_regvals_tvp (struct imstt_par *par, u_int bpp) set_imstt_regvals_tvp() argument
590 switch (bpp) { set_imstt_regvals_tvp()
656 set_imstt_regvals (struct fb_info *info, u_int bpp) set_imstt_regvals() argument
663 set_imstt_regvals_ibm(par, bpp); set_imstt_regvals()
665 set_imstt_regvals_tvp(par, bpp); set_imstt_regvals()
674 * 8bpp 0 0 set_imstt_regvals()
675 * 16bpp 0 1 set_imstt_regvals()
676 * 32bpp 1 1 set_imstt_regvals()
678 switch (bpp) { set_imstt_regvals()
883 u_int bpp = info->var.bits_per_pixel; imsttfb_setcolreg() local
893 if (0 && bpp == 16) /* screws up X */ imsttfb_setcolreg()
904 switch (bpp) { imsttfb_setcolreg()
H A Dvt8500lcdfb.c50 int reg_bpp = 5; /* 16bpp */ vt8500lcd_set_par()
282 u32 bpp; vt8500lcd_probe() local
354 ret = of_property_read_u32(pdev->dev.of_node, "bits-per-pixel", &bpp); vt8500lcd_probe()
359 fb_mem_len = of_mode.xres * of_mode.yres * 2 * (bpp / 8); vt8500lcd_probe()
409 fbi->fb.var.bits_per_pixel = bpp; vt8500lcd_probe()
H A Darkfb.c618 u32 bpp = info->var.bits_per_pixel; arkfb_set_par() local
621 if (bpp != 0) { arkfb_set_par()
623 info->fix.line_length = (info->var.xres_virtual * bpp) / 8; arkfb_set_par()
628 /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ arkfb_set_par()
629 info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); arkfb_set_par()
632 offset_value = (info->var.xres_virtual * bpp) / 64; arkfb_set_par()
732 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode */ arkfb_set_par()
748 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ arkfb_set_par()
755 vga_wseq(par->state.vgabase, 0x11, 0x1A); /* 16bpp accel mode */ arkfb_set_par()
762 vga_wseq(par->state.vgabase, 0x11, 0x16); /* 8bpp accel mode ??? */ arkfb_set_par()
771 vga_wseq(par->state.vgabase, 0x11, 0x1E); /* 32bpp accel mode */ arkfb_set_par()
H A Dbfin_adv7393fb.c161 fbdev->av1->x_modify = fbdev->modes[mode].bpp / 8; dma_desc_list()
165 1) * (fbdev->modes[mode].bpp / 8); dma_desc_list()
188 fbdev->av2->x_modify = (fbdev->modes[mode].bpp / 8); dma_desc_list()
193 1) * (fbdev->modes[mode].bpp / 8); dma_desc_list()
403 (fbdev->modes[mode].bpp / 8); bfin_adv7393_fb_probe()
406 fbdev->modes[mode].xres * (fbdev->modes[mode].bpp / 8); bfin_adv7393_fb_probe()
453 bfin_adv7393_fb_defined.bits_per_pixel = fbdev->modes[mode].bpp; bfin_adv7393_fb_probe()
H A Djz4740_fb.c224 if (jzfb->pdata->bpp == 18) jzfb_num_data_pins()
263 switch (jzfb->pdata->bpp) { jzfb_get_controller_bpp()
270 return jzfb->pdata->bpp; jzfb_get_controller_bpp()
294 var->bits_per_pixel != jzfb->pdata->bpp) jzfb_check_var()
303 switch (jzfb->pdata->bpp) { jzfb_check_var()
382 switch (pdata->bpp) { jzfb_set_par()
676 fb->var.bits_per_pixel = pdata->bpp; jzfb_probe()
H A Dimxfb.c367 var->bits_per_pixel = imxfb_mode->bpp; imxfb_check_var()
689 u32 bpp; imxfb_of_read_mode() local
702 ret = of_property_read_u32(np, "bits-per-pixel", &bpp); imxfb_of_read_mode()
706 dev_err(dev, "Failed to read bpp and pcr from DT\n"); imxfb_of_read_mode()
710 if (bpp < 1 || bpp > 255) { imxfb_of_read_mode()
715 imxfb_mode->bpp = bpp; imxfb_of_read_mode()
885 * be the same as m->bpp/8 */ imxfb_probe()
887 bytes_per_pixel = (m->bpp + 7) / 8; imxfb_probe()
H A Dsh_mobile_lcdcfb.c632 unsigned int bpp; member in struct:sh_mobile_lcdc_format_info
640 .bpp = 16,
645 .bpp = 24,
650 .bpp = 32,
655 .bpp = 12,
660 .bpp = 12,
665 .bpp = 16,
670 .bpp = 16,
675 .bpp = 24,
680 .bpp = 24,
1267 var->bits_per_pixel = format->bpp; __sh_mobile_lcdc_check_var()
1517 * ovl->format->bpp / 8; sh_mobile_lcdc_overlay_pan()
1520 unsigned int xsub = ovl->format->bpp < 24 ? 2 : 1; sh_mobile_lcdc_overlay_pan()
1521 unsigned int ysub = ovl->format->bpp < 16 ? 2 : 1; sh_mobile_lcdc_overlay_pan()
1589 ovl->pitch = info->var.xres_virtual * ovl->format->bpp / 8; sh_mobile_lcdc_overlay_set_par()
1753 var->bits_per_pixel = ovl->format->bpp; sh_mobile_lcdc_overlay_fb_init()
1832 * ch->format->bpp / 8; sh_mobile_lcdc_pan()
1835 unsigned int xsub = ch->format->bpp < 24 ? 2 : 1; sh_mobile_lcdc_pan()
1836 unsigned int ysub = ch->format->bpp < 16 ? 2 : 1; sh_mobile_lcdc_pan()
2047 ch->pitch = info->var.xres_virtual * ch->format->bpp / 8; sh_mobile_lcdc_set_par()
2263 var->bits_per_pixel = ch->format->bpp; sh_mobile_lcdc_channel_fb_init()
2575 ovl->pitch = ovl->xres_virtual * format->bpp / 8; sh_mobile_lcdc_overlay_init()
2581 * format->bpp / 8 * 2; sh_mobile_lcdc_overlay_init()
2665 ch->pitch = ch->xres_virtual * format->bpp / 8; sh_mobile_lcdc_channel_init()
2676 ch->fb_size = max_size * format->bpp / 8 * 2; sh_mobile_lcdc_channel_init()
H A Dsh_mipi_dsi.c136 int bpp; sh_mipi_setup() local
341 bpp = linelength / mode->xres; /* byte / pixel */ sh_mipi_setup()
342 if ((pdata->lane / div) > bpp) { sh_mipi_setup()
343 tmp = mode->xres / bpp; /* output cycle */ sh_mipi_setup()
H A Dsm712.h84 int bpp; member in struct:modeinit
/linux-4.4.14/drivers/gpu/drm/shmobile/
H A Dshmob_drm_kms.c34 .bpp = 16,
40 .bpp = 24,
46 .bpp = 32,
52 .bpp = 12,
58 .bpp = 12,
64 .bpp = 16,
70 .bpp = 16,
76 .bpp = 24,
82 .bpp = 24,
125 unsigned int chroma_cpp = format->bpp == 24 ? 2 : 1; shmob_drm_fb_create()
H A Dshmob_drm_kms.h24 unsigned int bpp; member in struct:shmob_drm_format_info
H A Dshmob_drm_plane.c50 unsigned int bpp; shmob_drm_plane_compute_base() local
52 bpp = splane->format->yuv ? 8 : splane->format->bpp; shmob_drm_plane_compute_base()
55 + y * fb->pitches[0] + x * bpp / 8; shmob_drm_plane_compute_base()
58 bpp = splane->format->bpp - 8; shmob_drm_plane_compute_base()
61 + y / (bpp == 4 ? 2 : 1) * fb->pitches[1] shmob_drm_plane_compute_base()
62 + x * (bpp == 16 ? 2 : 1); shmob_drm_plane_compute_base()
H A Dshmob_drm_crtc.c310 unsigned int bpp; shmob_drm_crtc_compute_base() local
312 bpp = scrtc->format->yuv ? 8 : scrtc->format->bpp; shmob_drm_crtc_compute_base()
315 + y * fb->pitches[0] + x * bpp / 8; shmob_drm_crtc_compute_base()
318 bpp = scrtc->format->bpp - 8; shmob_drm_crtc_compute_base()
321 + y / (bpp == 4 ? 2 : 1) * fb->pitches[1] shmob_drm_crtc_compute_base()
322 + x * (bpp == 16 ? 2 : 1); shmob_drm_crtc_compute_base()
/linux-4.4.14/include/video/
H A Dsh_mobile_lcdc.h105 RGB8 = LDMT1R_MIFTYP_RGB8, /* 24bpp, 8:8:8 */
106 RGB9 = LDMT1R_MIFTYP_RGB9, /* 18bpp, 9:9 */
107 RGB12A = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
108 RGB12B = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
109 RGB16 = LDMT1R_MIFTYP_RGB16, /* 16bpp */
110 RGB18 = LDMT1R_MIFTYP_RGB18, /* 18bpp */
111 RGB24 = LDMT1R_MIFTYP_RGB24, /* 24bpp */
112 YUV422 = LDMT1R_MIFTYP_YCBCR, /* 16bpp */
113 SYS8A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
114 SYS8B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
115 SYS8C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
116 SYS8D = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
117 SYS9 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9, /* 18bpp, 9:9 */
118 SYS12 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
119 SYS16A = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A, /* 16bpp */
120 SYS16B = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B, /* 18bpp, 16:2 */
121 SYS16C = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C, /* 18bpp, 2:16 */
122 SYS18 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
123 SYS24 = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
H A Dsa1100fb.h37 u_char bpp; member in struct:sa1100fb_mach_info
H A Dda8xx-fb.h51 int bpp; member in struct:lcd_ctrl_config
H A Dmbxfb.h19 struct mbxfb_val bpp; member in struct:mbxfb_platform_data
H A Dsstfb.h233 # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/
234 # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/
327 void (*set_vidmod) (struct fb_info *info, const int bpp);
/linux-4.4.14/drivers/video/fbdev/core/
H A Dfb_draw.h25 pixel_to_pat( u32 bpp, u32 pixel) pixel_to_pat() argument
27 switch (bpp) { pixel_to_pat()
45 WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp); pixel_to_pat()
51 pixel_to_pat( u32 bpp, u32 pixel) pixel_to_pat() argument
53 switch (bpp) { pixel_to_pat()
71 WARN(1, "pixel_to_pat(): unsupported pixelformat %d\n", bpp); pixel_to_pat()
147 unsigned bpp = info->var.bits_per_pixel; fb_compute_bswapmask() local
149 if ((bpp < 8) && (info->var.nonstd & FB_NONSTD_REV_PIX_IN_B)) { fb_compute_bswapmask()
152 * works only for 1, 2 and 4 bpp fb_compute_bswapmask()
154 bswapmask = 7 - bpp + 1; fb_compute_bswapmask()
H A Dcfbimgblt.c83 int i, n, bpp = p->var.bits_per_pixel; color_imageblit() local
84 u32 null_bits = 32 - bpp; color_imageblit()
108 color <<= FB_LEFT_POS(p, bpp); color_imageblit()
116 shift += bpp; color_imageblit()
143 u32 shift, color = 0, bpp = p->var.bits_per_pixel; slow_imageblit() local
146 u32 null_bits = 32 - bpp; slow_imageblit()
153 fgcolor <<= FB_LEFT_POS(p, bpp); slow_imageblit()
154 bgcolor <<= FB_LEFT_POS(p, bpp); slow_imageblit()
182 shift += bpp; slow_imageblit()
219 u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; fast_imageblit() local
220 u32 ppw = 32/bpp, spitch = (image->width + 7)/8; fast_imageblit()
227 switch (bpp) { fast_imageblit()
241 fgx <<= bpp; fast_imageblit() local
242 bgx <<= bpp; fast_imageblit() local
268 u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel; cfb_imageblit() local
276 bitstart = (dy * p->fix.line_length * 8) + (dx * bpp); cfb_imageblit()
297 if (32 % bpp == 0 && !start_index && !pitch_index && cfb_imageblit()
298 ((width & (32/bpp-1)) == 0) && cfb_imageblit()
299 bpp >= 8 && bpp <= 32) cfb_imageblit()
H A Dsysimgblt.c58 int i, n, bpp = p->var.bits_per_pixel; color_imageblit() local
59 u32 null_bits = 32 - bpp; color_imageblit()
82 color <<= FB_LEFT_POS(p, bpp); color_imageblit()
90 shift += bpp; color_imageblit()
115 u32 shift, color = 0, bpp = p->var.bits_per_pixel; slow_imageblit() local
118 u32 null_bits = 32 - bpp; slow_imageblit()
124 fgcolor <<= FB_LEFT_POS(p, bpp); slow_imageblit()
125 bgcolor <<= FB_LEFT_POS(p, bpp); slow_imageblit()
153 shift += bpp; slow_imageblit()
189 u32 fgx = fgcolor, bgx = bgcolor, bpp = p->var.bits_per_pixel; fast_imageblit() local
190 u32 ppw = 32/bpp, spitch = (image->width + 7)/8; fast_imageblit()
197 switch (bpp) { fast_imageblit()
211 fgx <<= bpp; fast_imageblit() local
212 bgx <<= bpp; fast_imageblit() local
243 u32 bpl = sizeof(u32), bpp = p->var.bits_per_pixel; sys_imageblit() local
251 bitstart = (dy * p->fix.line_length * 8) + (dx * bpp); sys_imageblit()
272 if (32 % bpp == 0 && !start_index && !pitch_index && sys_imageblit()
273 ((width & (32/bpp-1)) == 0) && sys_imageblit()
274 bpp >= 8 && bpp <= 32) sys_imageblit()
H A Dcfbfillrect.c283 u32 bpp = p->var.bits_per_pixel; cfb_fillrect() local
296 pat = pixel_to_pat(bpp, fg); cfb_fillrect()
300 dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp; cfb_fillrect()
301 /* FIXME For now we support 1-32 bpp only */ cfb_fillrect()
302 left = bits % bpp; cfb_fillrect()
327 fill_op32(p, dst, dst_idx, pat, width*bpp, bits, cfb_fillrect()
338 left = bpp - right; cfb_fillrect()
340 right = bpp - left; cfb_fillrect()
357 r = dst_idx % bpp; cfb_fillrect()
359 pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp)); cfb_fillrect()
361 width*bpp, bits); cfb_fillrect()
H A Dsysfillrect.c248 u32 bpp = p->var.bits_per_pixel; sys_fillrect() local
261 pat = pixel_to_pat( bpp, fg); sys_fillrect()
265 dst_idx += rect->dy*p->fix.line_length*8+rect->dx*bpp; sys_fillrect()
266 /* FIXME For now we support 1-32 bpp only */ sys_fillrect()
267 left = bits % bpp; sys_fillrect()
291 fill_op32(p, dst, dst_idx, pat, width*bpp, bits); sys_fillrect()
301 left = bpp - right; sys_fillrect()
303 right = bpp - left; sys_fillrect()
321 r = dst_idx % bpp; sys_fillrect()
323 pat2 = le_long_to_cpu(rolx(cpu_to_le_long(pat), r, bpp)); sys_fillrect()
325 width*bpp, bits); sys_fillrect()
H A Dmodedb.c591 * @bpp: color depth in bits per pixel
600 const struct fb_videomode *mode, unsigned int bpp) fb_try_mode()
606 mode->xres, mode->yres, bpp, mode->refresh); fb_try_mode()
613 var->bits_per_pixel = bpp; fb_try_mode()
647 * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m] or
648 * <name>[-<bpp>][@<refresh>]
650 * with <xres>, <yres>, <bpp> and <refresh> decimal numbers and
653 * If 'M' is present after yres (and before refresh/bpp if present),
699 unsigned int xres = 0, yres = 0, bpp = default_bpp, refresh = 0; fb_find_mode() local
721 bpp = simple_strtol(&name[i+1], NULL, fb_find_mode()
786 if (!ret && !fb_try_mode(var, info, &cvt_mode, bpp)) { fb_find_mode()
821 !fb_try_mode(var, info, &db[i], bpp)) { fb_find_mode()
832 fb_try_mode(var, info, &db[best], bpp); fb_find_mode()
841 if (!fb_try_mode(var, info, &db[i], bpp)) { fb_find_mode()
859 fb_try_mode(var, info, &db[best], bpp); fb_find_mode()
599 fb_try_mode(struct fb_var_screeninfo *var, struct fb_info *info, const struct fb_videomode *mode, unsigned int bpp) fb_try_mode() argument
/linux-4.4.14/drivers/gpu/drm/udl/
H A Dudl_transfer.c85 static inline u16 get_pixel_val16(const uint8_t *pixel, int bpp) get_pixel_val16() argument
88 if (bpp == 2) get_pixel_val16()
90 else if (bpp == 4) get_pixel_val16()
127 const uint8_t *const cmd_buffer_end, int bpp) udl_compress_hline16()
156 min((int)(pixel_end - pixel) / bpp, udl_compress_hline16()
157 (int)(cmd_buffer_end - cmd) / 2))) * bpp; udl_compress_hline16()
159 prefetch_range((void *) pixel, (cmd_pixel_end - pixel) * bpp); udl_compress_hline16()
160 pixel_val16 = get_pixel_val16(pixel, bpp); udl_compress_hline16()
169 pixel += bpp; udl_compress_hline16()
172 pixel_val16 = get_pixel_val16(pixel, bpp); udl_compress_hline16()
175 pixel += bpp; udl_compress_hline16()
178 if (unlikely(pixel > start + bpp)) { udl_compress_hline16()
181 raw_pixel_start) / bpp) + 1) & 0xFF; udl_compress_hline16()
184 *cmd++ = (((pixel - start) / bpp) - 1) & 0xFF; udl_compress_hline16()
194 *raw_pixels_count_byte = ((pixel-raw_pixel_start) / bpp) & 0xFF; udl_compress_hline16()
197 *cmd_pixels_count_byte = ((pixel - cmd_pixel_start) / bpp) & 0xFF; udl_compress_hline16()
198 dev_addr += ((pixel - cmd_pixel_start) / bpp) * 2; udl_compress_hline16()
221 int udl_render_hline(struct drm_device *dev, int bpp, struct urb **urb_ptr, udl_render_hline() argument
228 u32 base16 = 0 + (device_byte_offset / bpp) * 2; udl_render_hline()
233 BUG_ON(!(bpp == 2 || bpp == 4)); udl_render_hline()
243 (u8 **) &cmd, (u8 *) cmd_end, bpp); udl_render_hline()
122 udl_compress_hline16( const u8 **pixel_start_ptr, const u8 *const pixel_end, uint32_t *device_address_ptr, uint8_t **command_buffer_ptr, const uint8_t *const cmd_buffer_end, int bpp) udl_compress_hline16() argument
H A Dudl_fb.c43 /** Read the red component (0..255) of a 32 bpp colour. */
46 /** Read the green component (0..255) of a 32 bpp colour. */
49 /** Read the blue component (0..255) of a 32 bpp colour. */
52 /** Return red/green component of a 16 bpp colour number. */
55 /** Return green/blue component of a 16 bpp colour number. */
58 /** Return 8 bpp colour number from red, green and blue components. */
155 int bpp = (fb->base.bits_per_pixel / 8); udl_handle_damage() local
225 const int byte_offset = line_offset + (x * bpp); udl_handle_damage()
226 const int dev_byte_offset = (fb->base.width * bpp * i) + (x * bpp); udl_handle_damage()
227 if (udl_render_hline(dev, bpp, &urb, udl_handle_damage()
230 (x2 - x + 1) * bpp, udl_handle_damage()
246 atomic_add(width*height*bpp, &udl->bytes_rendered); udl_handle_damage()
H A Dudl_modeset.c84 * DisplayLink HW has separate 16bpp and 8bpp framebuffers.
85 * In 24bpp modes, the low 323 RGB bits go in the 8bpp framebuffer
328 * pointers, currently, we only * use the 16 bpp segment. udl_crtc_mode_set()
332 /* set base for 16bpp segment to 0 */ udl_crtc_mode_set()
334 /* set base for 8bpp segment to end of fb */ udl_crtc_mode_set()
/linux-4.4.14/drivers/video/fbdev/matrox/
H A Dmatroxfb_DAC1064.h66 #define M1064_XMULCTRL_DEPTH_8BPP 0x00 /* 8 bpp paletized */
67 #define M1064_XMULCTRL_DEPTH_15BPP_1BPP 0x01 /* 15 bpp paletized + 1 bpp overlay */
68 #define M1064_XMULCTRL_DEPTH_16BPP 0x02 /* 16 bpp paletized */
69 #define M1064_XMULCTRL_DEPTH_24BPP 0x03 /* 24 bpp paletized */
70 #define M1064_XMULCTRL_DEPTH_24BPP_8BPP 0x04 /* 24 bpp direct + 8 bpp overlay paletized */
71 #define M1064_XMULCTRL_2G8V16 0x05 /* 15 bpp video direct, half xres, 8bpp paletized */
72 #define M1064_XMULCTRL_G16V16 0x06 /* 15 bpp video, 15bpp graphics, one of them paletized */
73 #define M1064_XMULCTRL_DEPTH_32BPP 0x07 /* 24 bpp paletized + 8 bpp unused */
H A Dmatroxfb_base.c429 int bpp) matroxfb_get_final_bppShift()
435 bppshft2 = bpp; matroxfb_get_final_bppShift()
447 int xres, int bpp) matroxfb_test_and_set_rounding()
454 switch (bpp) { DBG()
480 int bpp) matroxfb_pitch_adjust()
487 if (!bpp) return xres; matroxfb_pitch_adjust()
493 if ((*width >= xres) && (matroxfb_test_and_set_rounding(minfo, *width, bpp) == *width)) { matroxfb_pitch_adjust()
500 xres_new = matroxfb_test_and_set_rounding(minfo, xres, bpp); matroxfb_pitch_adjust()
532 unsigned char bpp; matroxfb_decode_var() member in struct:RGBT
550 unsigned int bpp = var->bits_per_pixel; matroxfb_decode_var() local
556 switch (bpp) { DBG()
572 var->xres_virtual = matroxfb_pitch_adjust(minfo, var->xres_virtual, bpp);
573 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
575 var->yres_virtual = vramlen * 8 / (var->xres_virtual * bpp);
576 memlen = var->xres_virtual * bpp * var->yres_virtual / 8;
582 if (bpp == 24) {
586 unsigned int m1 = linelen = var->xres_virtual * bpp / 8;
615 if (bpp == 16 && var->green.length == 5) {
616 bpp--; /* an artificial value - 15 */
619 for (rgbt = table; rgbt->bpp < bpp; rgbt++);
630 if (bpp > 8)
711 fix->xpanstep = 8; /* 8 for 8bpp, 4 for 16bpp, 2 for 32bpp */ matroxfb_init_fix()
2511 MODULE_PARM_DESC(inv24, "Inverts clock polarity for 24bpp and loop frequency > 100MHz (default=do not invert polarity)");
2548 MODULE_PARM_DESC(grayscale, "Sets display into grayscale. Works perfectly with paletized videomode (4, 8bpp), some limitations apply to 16, 24 and 32bpp videomodes (default=nograyscale)");
428 matroxfb_get_final_bppShift(const struct matrox_fb_info *minfo, int bpp) matroxfb_get_final_bppShift() argument
446 matroxfb_test_and_set_rounding(const struct matrox_fb_info *minfo, int xres, int bpp) matroxfb_test_and_set_rounding() argument
479 matroxfb_pitch_adjust(const struct matrox_fb_info *minfo, int xres, int bpp) matroxfb_pitch_adjust() argument
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dsetup-fb-24bpp.c1 /* linux/arch/arm/plat-s3c64xx/setup-fb-24bpp.c
8 * Base S3C64XX setup information for 24bpp LCD framebuffer
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Dbf54x-lq043.h29 struct bfin_bf54xfb_val bpp; member in struct:bfin_bf54xfb_mach_info
/linux-4.4.14/drivers/gpu/drm/tilcdc/
H A Dtilcdc_external.c21 .bpp = 16,
55 static int tilcdc_add_external_encoder(struct drm_device *dev, int *bpp, tilcdc_add_external_encoder() argument
67 *bpp = panel_info_tda998x.bpp; tilcdc_add_external_encoder()
97 int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp) tilcdc_add_external_encoders() argument
111 ret = tilcdc_add_external_encoder(dev, bpp, connector); tilcdc_add_external_encoders()
H A Dtilcdc_external.h21 int tilcdc_add_external_encoders(struct drm_device *dev, int *bpp);
H A Dtilcdc_drv.c154 u32 bpp = 0; tilcdc_load() local
265 ret = tilcdc_add_external_encoders(dev, &bpp); tilcdc_load()
292 bpp = mod->preferred_bpp; tilcdc_load()
293 if (bpp > 0) tilcdc_load()
297 priv->fbdev = drm_fbdev_cma_init(dev, bpp, tilcdc_load()
H A Dtilcdc_crtc.c93 unsigned int depth, bpp; update_scanout() local
95 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp); update_scanout()
99 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8); update_scanout()
367 unsigned int depth, bpp; tilcdc_crtc_mode_set() local
369 drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp); tilcdc_crtc_mode_set()
370 switch (bpp) { tilcdc_crtc_mode_set()
H A Dtilcdc_panel.c327 ret |= of_property_read_u32(info_np, "bpp", &info->bpp); of_get_panel_info()
412 mod->preferred_bpp = panel_mod->info->bpp; panel_probe()
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Darb.c47 int bpp; member in struct:nv_sim_state
58 int pagemiss, cas, width, bpp; nv04_calc_arb() local
71 bpp = arb->bpp; nv04_calc_arb()
88 crtc_drain_rate = pclk_freq * bpp / 8; nv04_calc_arb()
98 p1 = p1 * bpp / 8; nv04_calc_arb()
128 drain_rate = pclk_freq * arb->bpp / 8; /* kB/s */ nv10_calc_arb()
165 + (arb->bpp == 32 ? 8 : 4); /* Margin of error. */ nv10_calc_arb()
197 nv04_update_arb(struct drm_device *dev, int VClk, int bpp, nv04_update_arb() argument
211 sim_data.bpp = bpp; nv04_update_arb()
253 nouveau_calc_arb(struct drm_device *dev, int vclk, int bpp, int *burst, int *lwm) nouveau_calc_arb() argument
258 nv04_update_arb(dev, vclk, bpp, burst, lwm); nouveau_calc_arb()
H A Dhw.h57 extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
390 nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp) nv_pitch_align() argument
395 if (bpp == 15) nv_pitch_align()
396 bpp = 16; nv_pitch_align()
397 if (bpp == 24) nv_pitch_align()
398 bpp = 8; nv_pitch_align()
402 mask = 128 / bpp - 1; nv_pitch_align()
404 mask = 512 / bpp - 1; nv_pitch_align()
/linux-4.4.14/drivers/gpu/drm/fsl-dcu/
H A Dfsl_dcu_drm_plane.c85 unsigned int alpha, bpp; fsl_dcu_drm_plane_atomic_update() local
99 bpp = FSL_DCU_RGB565; fsl_dcu_drm_plane_atomic_update()
103 bpp = FSL_DCU_RGB888; fsl_dcu_drm_plane_atomic_update()
107 bpp = FSL_DCU_ARGB8888; fsl_dcu_drm_plane_atomic_update()
111 bpp = FSL_DCU_ARGB4444; fsl_dcu_drm_plane_atomic_update()
115 bpp = FSL_DCU_ARGB1555; fsl_dcu_drm_plane_atomic_update()
119 bpp = FSL_DCU_YUV422; fsl_dcu_drm_plane_atomic_update()
143 DCU_LAYER_BPP(bpp) | fsl_dcu_drm_plane_atomic_update()
/linux-4.4.14/arch/arm/plat-samsung/include/plat/
H A Dfb.h29 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
31 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
H A Dfb-s3c2410.h35 unsigned short bpp; member in struct:s3c2410fb_display
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dlart.c34 .pixclock = 150000, .bpp = 4,
50 .pixclock = 150000, .bpp = 16,
63 .pixclock = 39721, .bpp = 16,
79 .pixclock = 63291, .bpp = 16,
H A Dshannon.c61 .pixclock = 152500, .bpp = 8,
H A Djornada720.c85 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
105 {0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
H A Dh3100.c63 .pixclock = 406977, .bpp = 4,
H A Dh3600.c74 .pixclock = 174757, .bpp = 16,
/linux-4.4.14/drivers/gpu/drm/armada/
H A Darmada_drm.h32 static inline uint32_t armada_pitch(uint32_t width, uint32_t bpp) armada_pitch() argument
34 uint32_t pitch = bpp != 4 ? width * ((bpp + 7) / 8) : width / 2; armada_pitch()
/linux-4.4.14/drivers/gpu/drm/bochs/
H A Dbochs_hw.c157 bochs->bpp = 32; bochs_hw_setmode()
158 bochs->stride = mode->hdisplay * (bochs->bpp / 8); bochs_hw_setmode()
161 DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n", bochs_hw_setmode()
162 bochs->xres, bochs->yres, bochs->bpp, bochs_hw_setmode()
168 bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP, bochs->bpp); bochs_hw_setmode()
187 x * (bochs->bpp / 8); bochs_hw_setbase()
189 int vx = (offset % bochs->stride) * 8 / bochs->bpp; bochs_hw_setbase()
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_dsi_pll.c43 int bpp; dsi_pixel_format_bpp() local
49 bpp = 24; dsi_pixel_format_bpp()
52 bpp = 18; dsi_pixel_format_bpp()
55 bpp = 16; dsi_pixel_format_bpp()
59 return bpp; dsi_pixel_format_bpp()
80 u32 bpp; dsi_rr_formula() local
89 bpp = dsi_pixel_format_bpp(pixel_format); dsi_rr_formula()
101 hsync_bytes = DIV_ROUND_UP(hsync * bpp, 8); dsi_rr_formula()
102 hbp_bytes = DIV_ROUND_UP(hbp * bpp, 8); dsi_rr_formula()
103 hactive_bytes = DIV_ROUND_UP(hactive * bpp, 8); dsi_rr_formula()
104 hfp_bytes = DIV_ROUND_UP(hfp * bpp, 8); dsi_rr_formula()
149 u32 bpp = dsi_pixel_format_bpp(pixel_format); dsi_clk_from_pclk() local
153 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); dsi_clk_from_pclk()
318 int bpp = dsi_pixel_format_bpp(pixel_format); assert_bpp_mismatch() local
320 WARN(bpp != pipe_bpp, assert_bpp_mismatch()
321 "bpp match assertion failure (expected %d, current %d)\n", assert_bpp_mismatch()
322 bpp, pipe_bpp); assert_bpp_mismatch()
H A Dintel_dsi.c761 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, txbyteclkhs() argument
764 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, txbyteclkhs()
776 unsigned int bpp = intel_crtc->config->pipe_bpp; set_dsi_timings() local
800 hactive = txbyteclkhs(hactive, bpp, lane_count, set_dsi_timings()
802 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); set_dsi_timings()
803 hsync = txbyteclkhs(hsync, bpp, lane_count, set_dsi_timings()
805 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); set_dsi_timings()
847 unsigned int bpp = intel_crtc->config->pipe_bpp; intel_dsi_prepare() local
916 /* XXX: cross-check bpp vs. pixel format? */ intel_dsi_prepare()
949 txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi_prepare()
956 bpp, intel_dsi->lane_count, intel_dsi_prepare()
/linux-4.4.14/fs/xfs/libxfs/
H A Dxfs_dir2_priv.h33 struct xfs_buf **bpp);
50 xfs_dablk_t bno, xfs_daddr_t mapped_bno, struct xfs_buf **bpp);
59 struct xfs_buf **bpp);
63 xfs_dablk_t fbno, xfs_daddr_t mappedbno, struct xfs_buf **bpp);
73 struct xfs_buf **bpp, __uint16_t magic);
117 xfs_dablk_t fbno, struct xfs_buf **bpp);
H A Dxfs_da_btree.h166 int level, struct xfs_buf **bpp, int whichfork);
189 struct xfs_buf **bpp, int which_fork);
202 struct xfs_buf **bpp, int whichfork,
/linux-4.4.14/include/linux/sunrpc/
H A Dcache.h91 char **bpp, int *blen);
238 extern void qword_add(char **bpp, int *lp, char *str);
239 extern void qword_addhex(char **bpp, int *lp, char *buf, int blen);
240 extern int qword_get(char **bpp, char *dest, int bufsize);
242 static inline int get_int(char **bpp, int *anint) get_int() argument
247 int len = qword_get(bpp, buf, sizeof(buf)); get_int()
262 static inline int get_uint(char **bpp, unsigned int *anint) get_uint() argument
265 int len = qword_get(bpp, buf, sizeof(buf)); get_uint()
278 static inline int get_time(char **bpp, time_t *time) get_time() argument
282 int len = qword_get(bpp, buf, sizeof(buf)); get_time()
296 static inline time_t get_expiry(char **bpp) get_expiry() argument
301 if (get_time(bpp, &rv)) get_expiry()
/linux-4.4.14/arch/arm/mach-nspire/
H A Dclcd.c38 .bpp = 16,
60 .bpp = 8,
90 panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8; nspire_clcd_setup()
/linux-4.4.14/drivers/gpu/drm/rcar-du/
H A Drcar_du_kms.h26 unsigned int bpp; member in struct:rcar_du_format_info
H A Drcar_du_kms.c39 .bpp = 16,
45 .bpp = 16,
51 .bpp = 16,
57 .bpp = 32,
63 .bpp = 32,
69 .bpp = 16,
75 .bpp = 16,
81 .bpp = 12,
87 .bpp = 12,
94 .bpp = 16,
121 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); rcar_du_dumb_create()
130 align = 16 * args->bpp / 8; rcar_du_dumb_create()
145 unsigned int bpp; rcar_du_fb_create() local
158 bpp = format->planes == 2 ? 1 : format->bpp / 8; rcar_du_fb_create()
159 max_pitch = 4096 * bpp; rcar_du_fb_create()
164 align = 16 * bpp; rcar_du_fb_create()
H A Drcar_du_plane.c62 * operation with 32bpp formats. rcar_du_plane_setup_fb()
67 mwr = fb->pitches[0] * 8 / state->format->bpp; rcar_du_plane_setup_fb()
69 if (interlaced && state->format->bpp == 32) rcar_du_plane_setup_fb()
75 * for 32bpp formats, according to the R8A7790 datasheet. No mention of rcar_du_plane_setup_fb()
88 (!interlaced && state->format->bpp == 32 ? 2 : 1)); rcar_du_plane_setup_fb()
100 (state->format->bpp == 16 ? 2 : 1) / 2); rcar_du_plane_setup_fb()
117 /* The PnALPHAR register controls alpha-blending in 16bpp formats rcar_du_plane_setup_mode()
/linux-4.4.14/drivers/video/fbdev/via/
H A Dvia_utility.h30 void viafb_set_gamma_table(int bpp, unsigned int *gamma_table);
32 void viafb_get_gamma_support_state(int bpp, unsigned int *support_state);
H A Dioctl.h99 unsigned short bpp; member in struct:device_t
120 u32 bpp; member in struct:viafb_ioctl_mode
169 /* bpp of first device */
173 /* bpp of second device */
201 int viafb_ioctl_hotplug(int hres, int vres, int bpp);
H A Dvia_utility.c132 void viafb_set_gamma_table(int bpp, unsigned int *gamma_table) viafb_set_gamma_table() argument
144 /* 8 bpp mode can't adjust gamma */ viafb_set_gamma_table()
145 if (bpp == 8) viafb_set_gamma_table()
236 void viafb_get_gamma_support_state(int bpp, unsigned int *support_state) viafb_get_gamma_support_state() argument
238 if (bpp == 8) viafb_get_gamma_support_state()
H A Dioctl.c81 int viafb_ioctl_hotplug(int hres, int vres, int bpp) viafb_ioctl_hotplug() argument
H A Daccel.c27 static int viafb_set_bpp(void __iomem *engine, u8 bpp) viafb_set_bpp() argument
34 switch (bpp) { viafb_set_bpp()
45 printk(KERN_WARNING "viafb_set_bpp: Unsupported bpp %d\n", bpp); viafb_set_bpp()
/linux-4.4.14/drivers/gpu/drm/gma500/
H A Doaktrail.h99 /* Bit0: 16bpp (not supported in LNC), */
100 /* Bit1: 18bpp loosely packed, */
101 /* Bit2: 18bpp packed, */
102 /* Bit3: 24bpp */
129 /* Bit0: 16bpp (not supported in LNC), */
130 /* Bit1: 18bpp loosely packed, */
131 /* Bit2: 18bpp packed, */
132 /* Bit3: 24bpp */
H A Dmdfld_dsi_dpi.c417 int num_lane, int bpp) mdfld_dsi_dpi_to_byte_clock_count()
419 return (u16)((pixel_clock_count * bpp) / (num_lane * 8)); mdfld_dsi_dpi_to_byte_clock_count()
430 int num_lane, int bpp) mdfld_dsi_dpi_timing_calculation()
446 * bclock_count = pclk_count * bpp / num_lane / 8 mdfld_dsi_dpi_timing_calculation()
449 pclk_hsync, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
451 pclk_hbp, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
453 pclk_hfp, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
455 pclk_hactive, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
457 pclk_vsync, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
459 pclk_vbp, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
461 pclk_vfp, num_lane, bpp); mdfld_dsi_dpi_timing_calculation()
488 switch (dsi_config->bpp) { mdfld_dsi_dpi_controller_init()
499 DRM_ERROR("unsupported color format, bpp = %d\n", mdfld_dsi_dpi_controller_init()
500 dsi_config->bpp); mdfld_dsi_dpi_controller_init()
505 (mode->vtotal * mode->htotal * dsi_config->bpp / mdfld_dsi_dpi_controller_init()
523 dsi_config->lane_count, dsi_config->bpp); mdfld_dsi_dpi_controller_init()
750 dsi_config->bpp); mdfld_mipi_set_video_timing()
416 mdfld_dsi_dpi_to_byte_clock_count(int pixel_clock_count, int num_lane, int bpp) mdfld_dsi_dpi_to_byte_clock_count() argument
428 mdfld_dsi_dpi_timing_calculation(struct drm_display_mode *mode, struct mdfld_dsi_dpi_timing *dpi_timing, int num_lane, int bpp) mdfld_dsi_dpi_timing_calculation() argument
H A Dframebuffer.c247 u32 bpp, depth; psb_framebuffer_init() local
250 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); psb_framebuffer_init()
254 switch (bpp) { psb_framebuffer_init()
349 u32 bpp, depth; psbfb_create() local
355 bpp = sizes->surface_bpp; psbfb_create()
359 if (bpp == 24) psbfb_create()
360 bpp = 32; psbfb_create()
368 mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((bpp + 7) / 8), 4096 >> pitch_lines); psbfb_create()
396 mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((bpp + 7) / 8), 64); psbfb_create()
418 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); psbfb_create()
H A Dintel_bios.c67 dev_priv->edp.bpp = 18; parse_edp()
71 dev_priv->edp.bpp); parse_edp()
79 dev_priv->edp.bpp = 18; parse_edp()
82 dev_priv->edp.bpp = 24; parse_edp()
85 dev_priv->edp.bpp = 30; parse_edp()
115 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); parse_edp()
H A Dmdfld_dsi_dpi.h60 int num_lane, int bpp);
H A Dcdv_intel_dp.c367 cdv_intel_dp_link_required(int pixel_clock, int bpp) cdv_intel_dp_link_required() argument
369 return (pixel_clock * bpp + 7) / 8; cdv_intel_dp_link_required()
528 (cdv_intel_dp_link_required(mode->clock, dev_priv->edp.bpp) cdv_intel_dp_mode_valid()
905 int bpp = 24; cdv_intel_dp_mode_fixup() local
910 bpp = dev_priv->edp.bpp; cdv_intel_dp_mode_fixup()
917 if (cdv_intel_dp_link_required(refclock, bpp) <= link_avail) { cdv_intel_dp_mode_fixup()
969 cdv_intel_dp_compute_m_n(int bpp, cdv_intel_dp_compute_m_n() argument
976 m_n->gmch_m = (pixel_clock * bpp + 7) >> 3; cdv_intel_dp_compute_m_n()
993 int lane_count = 4, bpp = 24; cdv_intel_dp_set_m_n() local
1014 bpp = dev_priv->edp.bpp; cdv_intel_dp_set_m_n()
1024 cdv_intel_dp_compute_m_n(bpp, lane_count, cdv_intel_dp_set_m_n()
/linux-4.4.14/arch/mips/include/asm/mach-jz4740/
H A Djz4740_fb.h42 * bpp: bits per pixel for the lcd
53 unsigned int bpp; member in struct:jz4740_fb_platform_data
/linux-4.4.14/drivers/video/fbdev/omap/
H A Dlcdc.c62 int bpp; member in struct:omap_lcd_controller
199 xelem = lcdc.xres * lcdc.bpp / 8 / esize; setup_lcd_dma()
209 xelem = lcdc.yres * lcdc.bpp / 16; setup_lcd_dma()
223 int bpp = lcdc.bpp; setup_lcd_dma() local
227 * YUV window embedded in a 16bpp frame buffer. setup_lcd_dma()
230 bpp = 16; setup_lcd_dma()
233 lcdc.screen_width * bpp / 8 / esize); setup_lcd_dma()
325 lcdc.bpp = 8; omap_lcdc_setup_plane()
330 lcdc.bpp = 16; omap_lcdc_setup_plane()
335 lcdc.bpp = 16; omap_lcdc_setup_plane()
341 lcdc.bpp = 12; omap_lcdc_setup_plane()
347 lcdc.bpp = 16; omap_lcdc_setup_plane()
483 l |= (is_tft && panel->bpp == 8) ? 0x810000 : 0; setup_regs()
634 int bpp; alloc_fbmem() local
638 bpp = panel->bpp; alloc_fbmem()
639 if (bpp == 12) alloc_fbmem()
640 bpp = 16; alloc_fbmem()
641 frame_size = PAGE_ALIGN(panel->x_res * bpp / 8 * panel->y_res); alloc_fbmem()
H A Domapfb_main.c158 int bpp = panel->bpp; ctrl_init() local
160 /* 12 bpp is packed in 16 bits */ ctrl_init()
161 if (bpp == 12) ctrl_init()
162 bpp = 16; ctrl_init()
163 def_size = def_vxres * def_vyres * bpp / 8; ctrl_init()
249 * palette if one is available. For now we support only 16bpp and thus store
387 int bpp; set_fb_fix() local
403 bpp = var->bits_per_pixel; set_fb_fix()
410 /* 12bpp is stored in 16 bits */ set_fb_fix()
411 bpp = 16; set_fb_fix()
421 fix->line_length = var->xres_virtual * bpp / 8; set_fb_fix()
462 if (plane->fbdev->panel->bpp == 12) set_color_mode()
479 int bpp; set_fb_var() local
491 bpp = var->bits_per_pixel; set_fb_var()
493 bpp = 16; set_fb_var()
536 line_size = var->xres_virtual * bpp / 8; set_fb_var()
540 var->xres_virtual = line_size * 8 / bpp; set_fb_var()
544 line_size = var->xres * bpp / 8; set_fb_var()
1496 var->bits_per_pixel = fbdev->panel->bpp; fbinfo_init()
H A Dlcd_h3.c76 .bpp = 16,
H A Dlcd_htcherald.c65 .bpp = 16,
H A Dlcd_inn1510.c60 .bpp = 16,
H A Dlcd_inn1610.c81 .bpp = 16,
H A Dlcd_osk.c81 .bpp = 16,
H A Dlcd_palmte.c59 .bpp = 8,
H A Dlcd_palmtt.c64 .bpp = 16,
H A Dlcd_palmz71.c60 .bpp = 16,
H A Dhwa742.c347 int bpp; send_frame_handler() local
363 bpp = 16; send_frame_handler()
368 bpp = 12; send_frame_handler()
373 bpp = 16; send_frame_handler()
396 offset = (scr_width * y + x) * bpp / 8; send_frame_handler()
812 /* time to transfer one pixel (16bpp) in ps */ setup_tearsync()
/linux-4.4.14/drivers/gpu/drm/cirrus/
H A Dcirrus_main.c56 u32 bpp, depth; cirrus_user_framebuffer_create() local
58 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); cirrus_user_framebuffer_create()
61 bpp, mode_cmd->pitches[0])) cirrus_user_framebuffer_create()
247 args->pitch = args->width * ((args->bpp + 7) / 8); cirrus_dumb_create()
311 int bpp, int pitch) cirrus_check_framebuffer()
316 if (bpp > cirrus_bpp) cirrus_check_framebuffer()
318 if (bpp > 32) cirrus_check_framebuffer()
310 cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height, int bpp, int pitch) cirrus_check_framebuffer() argument
H A Dcirrus_fbdev.c27 int bpp = (afbdev->gfb.base.bits_per_pixel + 7)/8; cirrus_dirty_update() local
87 src_offset = dst_offset = i * afbdev->gfb.base.pitches[0] + (x * bpp); cirrus_dirty_update()
88 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, width * bpp); cirrus_dirty_update()
143 u32 bpp, depth; cirrusfb_create_object() local
148 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); cirrusfb_create_object()
151 bpp, mode_cmd->pitches[0])) cirrusfb_create_object()
H A Dcirrus_drv.c23 MODULE_PARM_DESC(bpp, "Max bits-per-pixel (default:24)");
24 module_param_named(bpp, cirrus_bpp, int, 0400);
/linux-4.4.14/arch/arm/mach-pxa/
H A Dlpd270.c60 /* LCD - 16bpp Active TFT */
299 .bpp = 16,
321 .bpp = 16,
343 .bpp = 16,
365 .bpp = 16,
387 .bpp = 16,
409 .bpp = 16,
H A Dcm-x2xx.c201 .bpp = 8, cmx2xx_init_leds()
226 .bpp = 8,
250 .bpp = 8,
274 .bpp = 8,
298 .bpp = 16,
321 .bpp = 8,
H A Dam200epd.c49 .bpp = 16,
63 .bpp = 16,
77 .bpp = 16,
249 /* we divide since we told the LCD controller we're 16bpp */ am200_presetup_fb()
H A Dzylonite.c147 .bpp = 16,
161 .bpp = 16,
181 .bpp = 16,
194 .bpp = 16,
H A Dvpac270.c484 .bpp = 32, vpac270_rtc_init()
500 .bpp = 16, vpac270_rtc_init()
516 .bpp = 16, vpac270_rtc_init()
532 .bpp = 16, vpac270_rtc_init()
H A Dpalm27x.c92 .bpp = 16,
107 .bpp = 16,
122 .bpp = 16,
H A Dtrizeps4.c82 /* LCD - 16bpp Active TFT */
458 .bpp = 8,
482 .bpp = 8,
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dradeon_fb.c66 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled) radeon_align_pitch() argument
72 switch (bpp / 8) { radeon_align_pitch()
116 u32 bpp, depth; radeonfb_create_pinned_object() local
118 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); radeonfb_create_pinned_object()
121 mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp, radeonfb_create_pinned_object()
122 fb_tiled) * ((bpp + 1) / 8); radeonfb_create_pinned_object()
142 switch (bpp) { radeonfb_create_pinned_object()
206 /* avivo can't scanout real 24bpp */ radeonfb_create()
329 /* select 8 bpp console on RN50 or 16MB cards */ radeon_fbdev_init()
H A Datombios_dp.c308 int bpp) dp_get_max_dp_pix_clock()
310 return (link_rate * lane_num * 8) / bpp; dp_get_max_dp_pix_clock()
336 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); radeon_dp_get_dp_lane_number() local
343 max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); radeon_dp_get_dp_lane_number()
355 int bpp = convert_bpc_to_bpp(radeon_get_monitor_bpc(connector)); radeon_dp_get_dp_link_clock() local
363 max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp); radeon_dp_get_dp_link_clock()
366 max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp); radeon_dp_get_dp_link_clock()
370 max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp); radeon_dp_get_dp_link_clock()
306 dp_get_max_dp_pix_clock(int link_rate, int lane_num, int bpp) dp_get_max_dp_pix_clock() argument
/linux-4.4.14/arch/powerpc/sysdev/
H A Dfsl_soc.h33 unsigned int bpp);
/linux-4.4.14/arch/arm/mach-w90x900/include/mach/
H A Dregs-ldm.h241 /* Hardware cursor color ram register mapped to bpp = 0 */
244 /* Hardware cursor color ram register mapped to bpp = 1 */
247 /* Hardware cursor color ram register mapped to bpp = 2 */
250 /* Hardware cursor color ram register mapped to bpp = 3 */
/linux-4.4.14/drivers/video/fbdev/aty/
H A Dmach64_accel.c74 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ aty_init_engine()
212 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_copyarea()
264 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_fillrect()
333 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ atyfb_imageblit()
H A Dmach64_gx.c80 const union aty_pll *pll, u32 bpp, u32 accel) aty_set_dac_514()
91 0, 0x41, 0x03, 0x71, 0x45}, /* 8 bpp */ aty_set_dac_514()
99 switch (bpp) { aty_set_dac_514()
123 u32 bpp, union aty_pll *pll) aty_var_to_pll_514()
205 const union aty_pll *pll, u32 bpp, aty_set_dac_ATI68860_B()
214 switch (bpp) { aty_set_dac_ATI68860_B()
288 const union aty_pll *pll, u32 bpp, aty_set_dac_ATT21C498()
298 switch (bpp) { aty_set_dac_ATT21C498()
341 u32 bpp, union aty_pll *pll) aty_var_to_pll_18818()
497 u32 bpp, union aty_pll *pll) aty_var_to_pll_1703()
613 u32 bpp, union aty_pll *pll) aty_var_to_pll_8398()
737 u32 bpp, union aty_pll *pll) aty_var_to_pll_408()
884 const union aty_pll *pll, u32 bpp, aty_set_dac_unsupported()
79 aty_set_dac_514(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) aty_set_dac_514() argument
122 aty_var_to_pll_514(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_514() argument
204 aty_set_dac_ATI68860_B(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) aty_set_dac_ATI68860_B() argument
287 aty_set_dac_ATT21C498(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) aty_set_dac_ATT21C498() argument
340 aty_var_to_pll_18818(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_18818() argument
496 aty_var_to_pll_1703(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_1703() argument
612 aty_var_to_pll_8398(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_8398() argument
736 aty_var_to_pll_408(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_408() argument
883 aty_set_dac_unsupported(const struct fb_info *info, const union aty_pll *pll, u32 bpp, u32 accel) aty_set_dac_unsupported() argument
H A Dmach64_ct.c18 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
19 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
119 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) aty_dsp_gt() argument
132 if (bpp>=8) aty_dsp_gt()
133 divider = divider * (bpp >> 2); aty_dsp_gt()
137 if (bpp == 0) aty_dsp_gt()
175 /* if (bpp == 0) aty_dsp_gt()
250 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll) aty_var_to_pll_ct() argument
257 if (M64_HAS(GTB_DSP) && (err = aty_dsp_gt(info, bpp, &pll->ct))) aty_var_to_pll_ct()
H A Datyfb.h16 u32 bpp; member in struct:crtc
300 const union aty_pll * pll, u32 bpp, u32 accel);
315 int (*var_to_pll) (const struct fb_info * info, u32 vclk_per, u32 bpp, union aty_pll * pll);
H A Daty128fb.c427 u32 depth, bpp; member in struct:aty128_crtc
745 if (par->crtc.bpp == 24) { aty128_init_engine()
1048 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst; aty128_var_to_crtc() local
1062 bpp = var->bits_per_pixel; aty128_var_to_crtc()
1072 if (bpp != 16) aty128_var_to_crtc()
1073 depth = bpp; aty128_var_to_crtc()
1166 crtc->bpp = bpp; aty128_var_to_crtc()
1444 u32 n, d, bpp; aty128_ddafifo() local
1447 bpp = (depth+7) & ~7; aty128_ddafifo()
1450 d = pll->vclk * bpp; aty128_ddafifo()
1529 if (par->crtc.bpp == 32) aty128fb_set_par()
1531 else if (par->crtc.bpp == 16) aty128fb_set_par()
1538 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3; aty128fb_set_par()
1539 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR aty128fb_set_par()
1553 par->crtc.bpp, aty128fb_set_par()
1554 par->crtc.vxres*par->crtc.bpp/8); aty128fb_set_par()
1649 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3)) aty128fb_pan_display()
1652 if (par->crtc.bpp == 24) aty128fb_pan_display()
2309 } else if (par->crtc.bpp == 16) aty128fb_setcolreg()
2606 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
H A Datyfb_base.c788 static u32 calc_line_length(struct atyfb_par *par, u32 vxres, u32 bpp) calc_line_length() argument
790 u32 line_length = vxres * bpp / 8; calc_line_length()
804 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp; aty_var_to_crtc() local
818 bpp = var->bits_per_pixel; aty_var_to_crtc()
819 if (bpp == 16) aty_var_to_crtc()
820 bpp = (var->green.length == 5) ? 15 : 16; aty_var_to_crtc()
833 if (bpp <= 8) { aty_var_to_crtc()
834 bpp = 8; aty_var_to_crtc()
839 } else if (bpp <= 15) { aty_var_to_crtc()
840 bpp = 16; aty_var_to_crtc()
845 } else if (bpp <= 16) { aty_var_to_crtc()
846 bpp = 16; aty_var_to_crtc()
851 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) { aty_var_to_crtc()
852 bpp = 24; aty_var_to_crtc()
857 } else if (bpp <= 32) { aty_var_to_crtc()
858 bpp = 32; aty_var_to_crtc()
864 FAIL("invalid bpp"); aty_var_to_crtc()
866 line_length = calc_line_length(par, vxres, bpp); aty_var_to_crtc()
933 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5 aty_var_to_crtc()
958 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly; aty_var_to_crtc()
1013 crtc->bpp = bpp; aty_var_to_crtc()
1015 ((yoffset * line_length + xoffset * bpp / 8) / 8) | aty_var_to_crtc()
1016 ((line_length / bpp) << 22); aty_var_to_crtc()
1160 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync; aty_crtc_to_var() local
1199 bpp = 4; aty_crtc_to_var()
1211 bpp = 8; aty_crtc_to_var()
1222 bpp = 16; aty_crtc_to_var()
1233 bpp = 16; aty_crtc_to_var()
1244 bpp = 24; aty_crtc_to_var()
1255 bpp = 32; aty_crtc_to_var()
1275 var->bits_per_pixel = bpp; aty_crtc_to_var()
1580 u32 bpp = info->var.bits_per_pixel; set_off_pitch() local
1583 ((yoffset * line_length + xoffset * bpp / 8) / 8) | set_off_pitch()
1584 ((line_length / bpp) << 22); set_off_pitch()
4015 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
/linux-4.4.14/drivers/gpu/drm/qxl/
H A Dqxl_dumb.c41 pitch = args->width * ((args->bpp + 1) / 8); qxl_mode_dumb_create()
45 switch (args->bpp) { qxl_mode_dumb_create()
H A Dqxl_fb.c95 /* TODO: hard coding 32 bpp */ qxl_fb_dirty_flush()
295 int bpp; qxlfb_create_pinned_object() local
298 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &bpp, &depth); qxlfb_create_pinned_object()
303 * have a large enough surface0 for 1024x768 Xorg 32bpp mode */ qxlfb_create_pinned_object()
353 int bpp = sizes->surface_bpp; qxlfb_create() local
360 mode_cmd.pitches[0] = ALIGN(mode_cmd.width * ((bpp + 1) / 8), 64); qxlfb_create()
361 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); qxlfb_create()
/linux-4.4.14/drivers/gpu/drm/msm/mdp/mdp4/
H A Dmdp4_lcdc_encoder.c113 int bpp, nchan, swap; setup_phy() local
118 bpp = 3 * connector->display_info.bpc; setup_phy()
120 if (!bpp) setup_phy()
121 bpp = 18; setup_phy()
127 switch (bpp) { setup_phy()
226 dev_err(dev->dev, "unknown bpp: %d\n", bpp); setup_phy()
390 /* TODO: hard-coded for 18bpp: */ mdp4_lcdc_encoder_enable()
/linux-4.4.14/include/drm/
H A Dexynos_drm.h38 * @bpp: default bit per pixel.
45 unsigned int bpp; member in struct:exynos_drm_fimd_pdata
/linux-4.4.14/drivers/hid/
H A Dhid-picolcd_fb.c151 static int picolcd_fb_update_tile(u8 *vbitmap, const u8 *bitmap, int bpp, picolcd_fb_update_tile() argument
158 if (bpp == 1) { picolcd_fb_update_tile()
166 } else if (bpp == 8) { picolcd_fb_update_tile()
221 memset(fbdata->bitmap, 0, PICOLCDFB_SIZE*fbdata->bpp); picolcd_fb_reset()
261 fbdata->bpp, chip, tile)) picolcd_fb_update()
366 __u32 bpp = var->bits_per_pixel; picolcd_fb_check_var() local
372 if (bpp >= 8) { picolcd_fb_check_var()
390 if (info->var.bits_per_pixel == fbdata->bpp) picolcd_set_par()
425 fbdata->bpp = info->var.bits_per_pixel; picolcd_set_par()
547 fbdata->bpp = picolcdfb_var.bits_per_pixel; picolcd_init_framebuffer()
/linux-4.4.14/drivers/gpu/drm/atmel-hlcdc/
H A Datmel_hlcdc_plane.c35 * @bpp: bytes per pixel deduced from pixel_format
62 int bpp[ATMEL_HLCDC_MAX_PLANES]; member in struct:atmel_hlcdc_plane_state
632 state->bpp[i] = drm_format_plane_cpp(fb->pixel_format, i); atmel_hlcdc_plane_atomic_check()
633 if (!state->bpp[i]) atmel_hlcdc_plane_atomic_check()
641 state->bpp[i]; atmel_hlcdc_plane_atomic_check()
644 state->pstride[i] = -fb->pitches[i] - state->bpp[i]; atmel_hlcdc_plane_atomic_check()
650 xdiv) * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
652 state->bpp[i]) - fb->pitches[i]; atmel_hlcdc_plane_atomic_check()
653 state->pstride[i] = -2 * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
659 xdiv) * state->bpp[i]; atmel_hlcdc_plane_atomic_check()
662 (2 * state->bpp[i]); atmel_hlcdc_plane_atomic_check()
663 state->pstride[i] = fb->pitches[i] - state->bpp[i]; atmel_hlcdc_plane_atomic_check()
670 state->bpp[i]; atmel_hlcdc_plane_atomic_check()
673 state->bpp[i]); atmel_hlcdc_plane_atomic_check()
/linux-4.4.14/drivers/media/platform/am437x/
H A Dam437x-vpfe.c73 unsigned int bpp; member in struct:bus_format
84 * @bpp: Bytes per pixel (when stored in memory)
103 .l.bpp = 4,
105 .s.bpp = 2,
112 .l.bpp = 4,
114 .s.bpp = 2,
121 .l.bpp = 4,
123 .s.bpp = 2,
130 .l.bpp = 4,
132 .s.bpp = 2,
139 .l.bpp = 2,
141 .s.bpp = 1,
148 .l.bpp = 2,
150 .s.bpp = 1,
157 .l.bpp = 2,
159 .s.bpp = 1,
166 .l.bpp = 2,
168 .s.bpp = 1,
175 .l.bpp = 4,
177 .s.bpp = 2,
184 .l.bpp = 4,
186 .s.bpp = 2,
193 struct v4l2_format *format, unsigned int *bpp);
226 struct v4l2_pix_format *pix, unsigned int *bpp) mbus_to_pix()
235 *bpp = 1; mbus_to_pix()
242 *bpp = (bus_width == 10) ? fmt->l.bpp : fmt->s.bpp; mbus_to_pix()
245 pix->bytesperline = ALIGN(pix->width * *bpp, 32); mbus_to_pix()
338 int bpp) vpfe_ccdc_setwin()
349 horz_start = image_win->left * bpp; vpfe_ccdc_setwin()
350 horz_nr_pixels = (image_win->width * bpp) - 1; vpfe_ccdc_setwin()
828 struct v4l2_rect *win, unsigned int bpp) vpfe_ccdc_set_image_window()
832 ccdc->ccdc_cfg.bayer.bytesperpixel = bpp; vpfe_ccdc_set_image_window()
833 ccdc->ccdc_cfg.bayer.bytesperline = ALIGN(win->width * bpp, 32); vpfe_ccdc_set_image_window()
836 ccdc->ccdc_cfg.ycbcr.bytesperpixel = bpp; vpfe_ccdc_set_image_window()
837 ccdc->ccdc_cfg.ycbcr.bytesperline = ALIGN(win->width * bpp, 32); vpfe_ccdc_set_image_window()
1064 vpfe_ccdc_set_image_window(&vpfe->ccdc, &vpfe->crop, vpfe->bpp); vpfe_config_ccdc_image_format()
1143 ret = __vpfe_get_format(vpfe, &vpfe->fmt, &vpfe->bpp); vpfe_config_image_format()
1423 struct v4l2_format *format, unsigned int *bpp) __vpfe_get_format()
1443 mbus_to_pix(vpfe, &fmt.format, &format->fmt.pix, bpp); __vpfe_get_format()
1452 mbus_to_pix(vpfe, &mbus_fmt, &format->fmt.pix, bpp); __vpfe_get_format()
1458 "%s size %dx%d (%s) bytesperline = %d, size = %d, bpp = %d\n", __vpfe_get_format()
1461 format->fmt.pix.bytesperline, format->fmt.pix.sizeimage, *bpp); __vpfe_get_format()
1468 struct v4l2_format *format, unsigned int *bpp) __vpfe_set_format()
1490 mbus_to_pix(vpfe, &fmt.format, &format->fmt.pix, bpp); __vpfe_set_format()
1495 "%s size %dx%d (%s) bytesperline = %d, size = %d, bpp = %d\n", __vpfe_set_format()
1498 format->fmt.pix.bytesperline, format->fmt.pix.sizeimage, *bpp); __vpfe_set_format()
1556 unsigned int bpp; vpfe_try_fmt() local
1560 return __vpfe_get_format(vpfe, fmt, &bpp); vpfe_try_fmt()
1568 unsigned int bpp; vpfe_s_fmt() local
1588 ret = __vpfe_set_format(vpfe, fmt, &bpp); vpfe_s_fmt()
1597 vpfe->bpp = bpp; vpfe_s_fmt()
2174 vpfe_ccdc_set_image_window(&vpfe->ccdc, &r, vpfe->bpp); vpfe_s_selection()
224 mbus_to_pix(struct vpfe_device *vpfe, const struct v4l2_mbus_framefmt *mbus, struct v4l2_pix_format *pix, unsigned int *bpp) mbus_to_pix() argument
335 vpfe_ccdc_setwin(struct vpfe_ccdc *ccdc, struct v4l2_rect *image_win, enum ccdc_frmfmt frm_fmt, int bpp) vpfe_ccdc_setwin() argument
827 vpfe_ccdc_set_image_window(struct vpfe_ccdc *ccdc, struct v4l2_rect *win, unsigned int bpp) vpfe_ccdc_set_image_window() argument
1422 __vpfe_get_format(struct vpfe_device *vpfe, struct v4l2_format *format, unsigned int *bpp) __vpfe_get_format() argument
1467 __vpfe_set_format(struct vpfe_device *vpfe, struct v4l2_format *format, unsigned int *bpp) __vpfe_set_format() argument
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_fb.c67 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled) amdgpu_align_pitch() argument
72 switch (bpp / 8) { amdgpu_align_pitch()
116 u32 bpp, depth; amdgpufb_create_pinned_object() local
118 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); amdgpufb_create_pinned_object()
121 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, bpp, amdgpufb_create_pinned_object()
122 fb_tiled) * ((bpp + 1) / 8); amdgpufb_create_pinned_object()
337 /* select 8 bpp console on low vram cards */ amdgpu_fbdev_init()
H A Datombios_dp.c257 int bpp) amdgpu_atombios_dp_get_max_dp_pix_clock()
259 return (link_rate * lane_num * 8) / bpp; amdgpu_atombios_dp_get_max_dp_pix_clock()
272 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); amdgpu_atombios_dp_get_dp_lane_number() local
279 max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp); amdgpu_atombios_dp_get_dp_lane_number()
291 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector)); amdgpu_atombios_dp_get_dp_link_clock() local
299 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp); amdgpu_atombios_dp_get_dp_link_clock()
302 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp); amdgpu_atombios_dp_get_dp_link_clock()
306 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp); amdgpu_atombios_dp_get_dp_link_clock()
255 amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate, int lane_num, int bpp) amdgpu_atombios_dp_get_max_dp_pix_clock() argument
/linux-4.4.14/drivers/usb/gadget/function/
H A Duvc_v4l2.c58 u8 bpp; member in struct:uvc_format
96 fmt->fmt.pix.bytesperline = video->bpp * video->width / 8; uvc_v4l2_get_format()
127 bpl = format->bpp * fmt->fmt.pix.width / 8; uvc_v4l2_set_format()
131 video->bpp = format->bpp; uvc_v4l2_set_format()
H A Duvc.h112 u8 bpp; member in struct:uvc_video
/linux-4.4.14/drivers/media/platform/blackfin/
H A Dppi.c223 bytes_per_line = params->width * params->bpp / 8; ppi_set_params()
225 hcount = params->width * params->bpp / params->dlen; ppi_set_params()
226 hdelay = params->hdelay * params->bpp / params->dlen; ppi_set_params()
227 samples_per_line = params->line * params->bpp / params->dlen; ppi_set_params()
288 * params->bpp / params->dlen; ppi_set_params()
H A Dbfin_capture.c52 int bpp; /* bits per pixel */ member in struct:bcap_format
83 int bpp; member in struct:bcap_device
115 .bpp = 16,
122 .bpp = 16,
129 .bpp = 16,
136 .bpp = 16,
143 .bpp = 16,
286 params.bpp = bcap_dev->bpp; bcap_start_streaming()
642 pixfmt->bytesperline = pixfmt->width * fmt->bpp / 8; bcap_try_format()
706 bcap_dev->bpp = bcap_fmt.bpp; bcap_s_fmt_vid_cap()
/linux-4.4.14/drivers/gpu/ipu-v3/
H A Dipu-cpmem.c295 int bpp = 0, npb = 0, ro, go, bo, to; ipu_cpmem_set_format_rgb() local
321 bpp = 0; ipu_cpmem_set_format_rgb()
325 bpp = 1; ipu_cpmem_set_format_rgb()
329 bpp = 3; ipu_cpmem_set_format_rgb()
333 bpp = 5; ipu_cpmem_set_format_rgb()
339 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); ipu_cpmem_set_format_rgb()
349 int bpp = 0, npb = 0; ipu_cpmem_set_format_passthrough() local
353 bpp = 0; ipu_cpmem_set_format_passthrough()
357 bpp = 1; ipu_cpmem_set_format_passthrough()
361 bpp = 3; ipu_cpmem_set_format_passthrough()
365 bpp = 5; ipu_cpmem_set_format_passthrough()
372 ipu_ch_param_write_field(ch, IPU_FIELD_BPP, bpp); ipu_cpmem_set_format_passthrough()
/linux-4.4.14/include/uapi/drm/
H A Ddrm_fourcc.h37 /* 8 bpp Red */
40 /* 16 bpp RG */
44 /* 8 bpp RGB */
48 /* 16 bpp RGB */
72 /* 24 bpp RGB */
76 /* 32 bpp RGB */
/linux-4.4.14/arch/m32r/include/asm/
H A Ds1d13806.h188 {0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
196 {0x0060,0x05}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp)
/linux-4.4.14/drivers/video/fbdev/kyro/
H A DSTG4000Ramdac.c46 /* Set LUT not used from 16bpp to 32 bpp ??? */ InitialiseRamdac()
H A Dfbdev.c48 /* 640x480, 16bpp @ 60 Hz */
388 static inline unsigned long get_line_length(int x, int bpp) get_line_length() argument
390 return (unsigned long)((((x*bpp)+31)&~31) >> 3); get_line_length()
490 /* time for a frame in ns (precision in 32bpp) */ kyrofb_set_par()
/linux-4.4.14/drivers/media/platform/vsp1/
H A Dvsp1_video.h30 * @bpp: bits per pixel
44 unsigned int bpp[3]; member in struct:vsp1_format_info
/linux-4.4.14/drivers/staging/media/omap4iss/
H A Diss_video.c35 V4L2_PIX_FMT_GREY, 8, "Greyscale 8 bpp", },
38 V4L2_PIX_FMT_Y10, 10, "Greyscale 10 bpp", },
41 V4L2_PIX_FMT_Y12, 12, "Greyscale 12 bpp", },
44 V4L2_PIX_FMT_SBGGR8, 8, "BGGR Bayer 8 bpp", },
47 V4L2_PIX_FMT_SGBRG8, 8, "GBRG Bayer 8 bpp", },
50 V4L2_PIX_FMT_SGRBG8, 8, "GRBG Bayer 8 bpp", },
53 V4L2_PIX_FMT_SRGGB8, 8, "RGGB Bayer 8 bpp", },
56 V4L2_PIX_FMT_SGRBG10DPCM8, 8, "GRBG Bayer 10 bpp DPCM8", },
59 V4L2_PIX_FMT_SBGGR10, 10, "BGGR Bayer 10 bpp", },
62 V4L2_PIX_FMT_SGBRG10, 10, "GBRG Bayer 10 bpp", },
65 V4L2_PIX_FMT_SGRBG10, 10, "GRBG Bayer 10 bpp", },
68 V4L2_PIX_FMT_SRGGB10, 10, "RGGB Bayer 10 bpp", },
71 V4L2_PIX_FMT_SBGGR12, 12, "BGGR Bayer 12 bpp", },
74 V4L2_PIX_FMT_SGBRG12, 12, "GBRG Bayer 12 bpp", },
77 V4L2_PIX_FMT_SGRBG12, 12, "GRBG Bayer 12 bpp", },
80 V4L2_PIX_FMT_SRGGB12, 12, "RGGB Bayer 12 bpp", },
137 min_bpl = pix->width * ALIGN(formats[i].bpp, 8) / 8; iss_video_mbus_to_pix()
/linux-4.4.14/drivers/gpu/drm/vc4/
H A Dvc4_bo.c34 int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8); vc4_dumb_create()
H A Dvc4_regs.h495 /* 8bpp */
497 /* 16bpp */
502 /* 24bpp */
505 /* 32bpp */
/linux-4.4.14/drivers/media/platform/soc_camera/
H A Dsoc_mediabus.c103 .name = "RGB666/32bpp",
112 .name = "RGB888/32bpp",
121 .name = "RGB888/32bpp",
130 .name = "RGB888/32bpp",
/linux-4.4.14/drivers/gpu/drm/mgag200/
H A Dmgag200_fb.c29 int bpp = (mfbdev->mfb.base.bits_per_pixel + 7)/8; mga_dirty_update() local
90 src_offset = dst_offset = i * mfbdev->mfb.base.pitches[0] + (x * bpp); mga_dirty_update()
91 memcpy_toio(bo->kmap.virtual + src_offset, mfbdev->sysram + src_offset, (x2 - x + 1) * bpp); mga_dirty_update()
275 /* prefer 16bpp on low end gpus with limited VRAM */ mgag200_fbdev_init()
H A Dmgag200_mode.c1142 u32 bpp; mga_crtc_mode_set() local
1146 bpp = 32; mga_crtc_mode_set()
1148 bpp = 16; mga_crtc_mode_set()
1150 bpp = 8; mga_crtc_mode_set()
1152 mb = (mode->clock * bpp) / 1000; mga_crtc_mode_set()
1594 int bpp = 32; mga_vga_mode_valid() local
1602 if (mga_vga_calculate_mode_bandwidth(mode, bpp) mga_vga_mode_valid()
1610 if (mga_vga_calculate_mode_bandwidth(mode, bpp) mga_vga_mode_valid()
1620 bpp > (31877 * 1024))) mga_vga_mode_valid()
1623 (mga_vga_calculate_mode_bandwidth(mode, bpp) mga_vga_mode_valid()
1627 (mga_vga_calculate_mode_bandwidth(mode, bpp) mga_vga_mode_valid()
1632 bpp) > (55000 * 1024))) { mga_vga_mode_valid()
1651 bpp = connector->cmdline_mode.bpp; mga_vga_mode_valid()
1654 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { mga_vga_mode_valid()
/linux-4.4.14/arch/x86/boot/
H A Dvesa.h48 u8 bpp; /* 25 */ member in struct:vesa_mode_info
H A Dvideo-vesa.c95 mi->depth = vminfo.bpp; vesa_probe()
219 boot_params.screen_info.lfb_depth = vminfo.bpp; vesa_store_mode_params_graphics()
228 if (vminfo.bpp <= 8) vesa_store_mode_params_graphics()
/linux-4.4.14/sound/usb/caiaq/
H A Ddevice.c264 int rate, int depth, int bpp) snd_usb_caiaq_set_audio_params()
285 tmp[2] = bpp & 0xff; snd_usb_caiaq_set_audio_params()
286 tmp[3] = bpp >> 8; snd_usb_caiaq_set_audio_params()
289 dev_dbg(dev, "setting audio params: %d Hz, %d bits, %d bpp\n", snd_usb_caiaq_set_audio_params()
290 rate, depth, bpp); snd_usb_caiaq_set_audio_params()
306 cdev->bpp = bpp; snd_usb_caiaq_set_audio_params()
263 snd_usb_caiaq_set_audio_params(struct snd_usb_caiaqdev *cdev, int rate, int depth, int bpp) snd_usb_caiaq_set_audio_params() argument
H A Daudio.c207 int bytes_per_sample, bpp, ret, i; snd_usb_caiaq_pcm_prepare() local
266 bpp = ((runtime->rate / 8000) + CLOCK_DRIFT_TOLERANCE) snd_usb_caiaq_pcm_prepare()
269 if (bpp > MAX_ENDPOINT_SIZE) snd_usb_caiaq_pcm_prepare()
270 bpp = MAX_ENDPOINT_SIZE; snd_usb_caiaq_pcm_prepare()
273 runtime->sample_bits, bpp); snd_usb_caiaq_pcm_prepare()
517 if (iso->actual_length < cdev->bpp) read_in_urb()
/linux-4.4.14/fs/nfsd/
H A Dnfs4idmap.c125 idtoname_request(struct cache_detail *cd, struct cache_head *ch, char **bpp, idtoname_request() argument
131 qword_add(bpp, blen, ent->authname); idtoname_request()
133 qword_add(bpp, blen, ent->type == IDMAP_TYPE_GROUP ? "group" : "user"); idtoname_request()
134 qword_add(bpp, blen, idstr); idtoname_request()
136 (*bpp)[-1] = '\n'; idtoname_request()
298 nametoid_request(struct cache_detail *cd, struct cache_head *ch, char **bpp, nametoid_request() argument
303 qword_add(bpp, blen, ent->authname); nametoid_request()
304 qword_add(bpp, blen, ent->type == IDMAP_TYPE_GROUP ? "group" : "user"); nametoid_request()
305 qword_add(bpp, blen, ent->name); nametoid_request()
307 (*bpp)[-1] = '\n'; nametoid_request()
H A Dexport.c53 char **bpp, int *blen) expkey_request()
59 qword_add(bpp, blen, ek->ek_client->name); expkey_request()
61 qword_add(bpp, blen, type); expkey_request()
62 qword_addhex(bpp, blen, (char*)ek->ek_fsid, key_len(ek->ek_fsidtype)); expkey_request()
63 (*bpp)[-1] = '\n'; expkey_request()
321 char **bpp, int *blen) svc_export_request()
327 qword_add(bpp, blen, exp->ex_client->name); svc_export_request()
328 pth = d_path(&exp->ex_path, *bpp, *blen); svc_export_request()
331 (*bpp)[0] = '\n'; svc_export_request()
334 qword_add(bpp, blen, pth); svc_export_request()
335 (*bpp)[-1] = '\n'; svc_export_request()
51 expkey_request(struct cache_detail *cd, struct cache_head *h, char **bpp, int *blen) expkey_request() argument
319 svc_export_request(struct cache_detail *cd, struct cache_head *h, char **bpp, int *blen) svc_export_request() argument
/linux-4.4.14/drivers/video/fbdev/geode/
H A Dgx1fb_core.c87 static int gx1_line_delta(int xres, int bpp) gx1_line_delta() argument
89 int line_delta = xres * (bpp >> 3); gx1_line_delta()
111 /* Only 16 bpp and 8 bpp is supported by the hardware. */ gx1fb_check_var()
465 MODULE_PARM_DESC(mode, "video mode (<x>x<y>[-<bpp>][@<refr>])");
H A Ddisplay_gx.c55 int gx_line_delta(int xres, int bpp) gx_line_delta() argument
58 return (xres * (bpp >> 3) + 7) & ~0x7; gx_line_delta()
/linux-4.4.14/drivers/video/fbdev/nvidia/
H A Dnv_hw.c244 int data, pagemiss, cas, width, video_enable, bpp; nv4CalcArbitration() local
259 bpp = arb->pix_bpp; nv4CalcArbitration()
296 crtc_drain_rate = pclk_freq * bpp / 8; nv4CalcArbitration()
332 crtc_drain_rate = pclk_freq * bpp / 8; nv4CalcArbitration()
343 p1 = p1 * bpp / 8; nv4CalcArbitration()
417 int data, pagemiss, width, video_enable, bpp; nv10CalcArbitration() local
437 bpp = arb->pix_bpp; nv10CalcArbitration()
468 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ nv10CalcArbitration()
471 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ nv10CalcArbitration()
508 crtc_drain_rate = pclk_freq * bpp / 8; /* MB/s */ nv10CalcArbitration()
535 /* bpp * pclk/8 */ nv10CalcArbitration()
536 crtc_drain_rate = pclk_freq * bpp / 8; nv10CalcArbitration()
577 p2 = p1clk * bpp / 8; /* bytes drained. */ nv10CalcArbitration()
857 int bpp, NVCalcStateExt()
865 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ NVCalcStateExt()
871 pixelDepth = (bpp + 1) / 8; NVCalcStateExt()
891 state->general = bpp == 16 ? 0x00101100 : 0x00100100; NVCalcStateExt()
933 state->general = bpp == 16 ? 0x00101100 : 0x00100100; NVCalcStateExt()
938 if (bpp != 8) /* DirectColor */ NVCalcStateExt()
855 NVCalcStateExt(struct nvidia_par *par, RIVA_HW_STATE * state, int bpp, int width, int hDisplaySize, int height, int dotClock, int flags) NVCalcStateExt() argument
H A Dnvidia.c74 static int bpp = 8; variable
180 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) { nvidia_panel_tweak()
1117 switch (bpp) { nvidia_set_fbinfo()
1119 bpp = 8; nvidia_set_fbinfo()
1122 bpp = 16; nvidia_set_fbinfo()
1125 bpp = 32; nvidia_set_fbinfo()
1134 nvidiafb_default_var.bits_per_pixel = bpp; nvidia_set_fbinfo()
1141 specs->modedb_len, &modedb, bpp); nvidia_set_fbinfo()
1146 specs->modedb, specs->modedb_len, &modedb, bpp); nvidia_set_fbinfo()
1487 } else if (!strncmp(this_opt, "bpp:", 4)) { nvidiafb_setup()
1488 bpp = simple_strtoul(this_opt+4, NULL, 0); nvidiafb_setup()
1567 module_param(bpp, int, 0);
1568 MODULE_PARM_DESC(bpp, "pixel width in bits"
H A Dnv_type.h53 u32 bpp; member in struct:_riva_hw_state
/linux-4.4.14/drivers/gpu/drm/ast/
H A Dast_fb.c53 int bpp = (afbdev->afb.base.bits_per_pixel + 7)/8; ast_dirty_update() local
114 src_offset = dst_offset = i * afbdev->afb.base.pitches[0] + (x * bpp); ast_dirty_update()
115 memcpy_toio(bo->kmap.virtual + src_offset, afbdev->sysram + src_offset, (x2 - x + 1) * bpp); ast_dirty_update()
170 u32 bpp, depth; astfb_create_object() local
175 drm_fb_get_bpp_depth(mode_cmd->pixel_format, &depth, &bpp); astfb_create_object()
/linux-4.4.14/drivers/staging/xgifb/
H A DXGI_main_26.c242 && (XGIbios_mode[i].bpp == 8)) { XGIfb_GetXG21DefaultLVDSModeIdx()
256 unsigned int bpp; XGIfb_search_mode() local
259 if (sscanf(name, "%ux%ux%u", &xres, &yres, &bpp) != 3) XGIfb_search_mode()
262 if (bpp == 24) XGIfb_search_mode()
263 bpp = 32; /* That's for people who mix up color and fb depth. */ XGIfb_search_mode()
268 XGIbios_mode[i].bpp == bpp) { XGIfb_search_mode()
315 if (XGIbios_mode[myindex].bpp > 8) XGIfb_validate_mode()
499 if (XGIbios_mode[myindex].bpp == 32) XGIfb_validate_mode()
517 XGIbios_mode[myindex].bpp / 8; XGIfb_validate_mode()
704 * in 8bpp Modes XGIfb_post_setmode()
712 * in 8bpp Modes if using LCD XGIfb_post_setmode()
974 (XGIbios_mode[xgifb_info->mode_idx].bpp XGIfb_do_set_var()
1026 XGIbios_mode[xgifb_info->mode_idx].bpp, XGIfb_do_set_var()
1029 xgifb_info->video_bpp = XGIbios_mode[xgifb_info->mode_idx].bpp; XGIfb_do_set_var()
1087 /* calculate base bpp dep. */ XGIfb_pan_var()
1278 (XGIbios_mode[search_idx].bpp == var->bits_per_pixel)) { XGIfb_check_var()
1296 XGIbios_mode[search_idx].bpp)) { XGIfb_check_var()
1922 xgifb_info->video_bpp = XGIbios_mode[xgifb_info->mode_idx].bpp; xgifb_probe()
/linux-4.4.14/drivers/media/pci/ivtv/
H A Divtvfb.c6 support for 8, 16 & 32 bpp packed pixel formats with alpha channel. In 16bpp
10 the initial resolution is either 640x400 (NTSC) or 640x480 (PAL) at 8bpp.
550 IVTVFB_DEBUG_WARN("ivtvfb_set_var - Invalid bpp\n"); ivtvfb_set_var()
554 IVTVFB_DEBUG_WARN("ivtvfb_set_var - Invalid bpp\n"); ivtvfb_set_var()
730 /* Max horizontal size is 1023 @ 32bpp, 2046 & 16bpp, 4092 @ 8bpp */ _ivtvfb_check_var()
744 IVTVFB_DEBUG_WARN("Invalid resolution for 8bpp: %d\n", var->xres); _ivtvfb_check_var()
748 IVTVFB_DEBUG_WARN("Invalid virtual resolution for 8bpp: %d)\n", var->xres_virtual); _ivtvfb_check_var()
755 IVTVFB_DEBUG_WARN("Invalid resolution for 16bpp: %d\n", var->xres); _ivtvfb_check_var()
759 IVTVFB_DEBUG_WARN("Invalid virtual resolution for 16bpp: %d)\n", var->xres_virtual); _ivtvfb_check_var()
995 /* Must be a multiple of 4 for 8bpp & 2 for 16bpp */ ivtvfb_init_vidmode()
/linux-4.4.14/drivers/gpu/drm/exynos/
H A Dexynos5433_drm_decon.c219 DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel); decon_win_set_pixfmt()
265 unsigned int bpp = state->fb->bits_per_pixel >> 3; decon_update_plane() local
293 val = BIT_VAL(pitch - plane->crtc_w * bpp, 27, 14) decon_update_plane()
294 | BIT_VAL(plane->crtc_w * bpp, 13, 0); decon_update_plane()
296 val = BIT_VAL(pitch - plane->crtc_w * bpp, 29, 15) decon_update_plane()
297 | BIT_VAL(plane->crtc_w * bpp, 14, 0); decon_update_plane()
/linux-4.4.14/drivers/video/fbdev/riva/
H A Driva_hw.c659 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; nv4CalcArbitration() local
676 bpp = arb->pix_bpp; nv4CalcArbitration()
716 crtc_drain_rate = pclk_freq * bpp/8; nv4CalcArbitration()
747 crtc_drain_rate = pclk_freq * bpp/8; nv4CalcArbitration()
757 p1 = p1 * bpp / 8; nv4CalcArbitration()
845 int data, pagemiss, cas,width, video_enable, color_key_enable, bpp, align; nv10CalcArbitration() local
867 bpp = arb->pix_bpp; nv10CalcArbitration()
904 mclk_extra = (bpp == 32) ? 31 : 42; /* Margin of error */ nv10CalcArbitration()
909 mclk_extra = (bpp == 32) ? 8 : 4; /* Margin of error */ nv10CalcArbitration()
946 crtc_drain_rate = pclk_freq * bpp/8; /* MB/s */ nv10CalcArbitration()
969 crtc_drain_rate = pclk_freq * bpp/8; /* bpp * pclk/8 */ nv10CalcArbitration()
1025 p2 = p1clk * bpp / 8; /* bytes drained. */ nv10CalcArbitration()
1237 int bpp, CalcStateExt()
1251 state->bpp = bpp; /* this is not bitsPerPixel, it's 8,15,16,32 */ CalcStateExt()
1257 pixelDepth = (bpp + 1)/8; CalcStateExt()
1290 state->general = bpp == 16 ? 0x00101100 : 0x00100100; CalcStateExt()
1316 state->general = bpp == 16 ? 0x00101100 : 0x00100100; CalcStateExt()
1323 if((bpp != 8) && (chip->Architecture != NV_ARCH_03)) CalcStateExt()
1427 switch (state->bpp) LoadStateExt()
1467 switch (state->bpp) LoadStateExt()
1513 switch (state->bpp) LoadStateExt()
1233 CalcStateExt( RIVA_HW_INST *chip, RIVA_HW_STATE *state, int bpp, int width, int hDisplaySize, int height, int dotClock ) CalcStateExt() argument
/linux-4.4.14/drivers/video/fbdev/omap2/dss/
H A Doverlay.c193 * RGB12U or RGB16 mode, and video port width interface is 18bpp or 24bpp
H A Drfbi.c634 static int rfbi_configure_bus(int rfbi_module, int bpp, int lines) rfbi_configure_bus() argument
642 switch (bpp) { rfbi_configure_bus()
680 if ((bpp % lines) == 0) { rfbi_configure_bus()
681 switch (bpp / lines) { rfbi_configure_bus()
695 } else if ((2 * bpp % lines) == 0) { rfbi_configure_bus()
696 if ((2 * bpp / lines) == 3) rfbi_configure_bus()
760 DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n", rfbi_configure_bus()
761 bpp, lines, cycle1, cycle2, cycle3); rfbi_configure_bus()
/linux-4.4.14/arch/parisc/include/asm/
H A Dgrfioctl.h85 unsigned int bpp, bppu; /* bits per pixel and used bpp */ member in struct:grf_fbinfo
/linux-4.4.14/drivers/video/fbdev/sis/
H A Dsis_accel.h193 #define SiS300SetupDSTColorDepth(bpp) \
195 MMIO_OUT16(ivideo->mmio_vbase, BR(1)+2, bpp);\
323 #define SiS310SetupDSTColorDepth(bpp) \
325 MMIO_OUT16(ivideo->mmio_vbase, AGP_BASE, bpp);\
/linux-4.4.14/drivers/media/platform/omap/
H A Domap_vout_vrfb.c213 vout->pix.height, vout->bpp, yuv_mode); omap_vout_vrfb_buffer_setup()
237 pixsize = vout->bpp * vout->vrfb_bpp; omap_vout_prepare_vrfb()
244 (vout->pix.width * vout->bpp)) + 1; omap_vout_prepare_vrfb()
251 elem_count = vout->pix.width * vout->bpp; omap_vout_prepare_vrfb()
H A Domap_vout.c152 int ifmt, bpp = 0; omap_vout_try_format() local
174 bpp = YUYV_BPP; omap_vout_try_format()
179 bpp = RGB565_BPP; omap_vout_try_format()
183 bpp = RGB24_BPP; omap_vout_try_format()
188 bpp = RGB32_BPP; omap_vout_try_format()
191 pix->bytesperline = pix->width * bpp; omap_vout_try_format()
194 return bpp; omap_vout_try_format()
687 *size = PAGE_ALIGN(vout->pix.width * vout->pix.height * vout->bpp); omap_vout_buffer_setup()
767 vb->size = vb->width * vb->height * vout->bpp; omap_vout_buffer_prepare()
1108 int ret, bpp; vidioc_s_fmt_vid_out() local
1151 bpp = omap_vout_try_format(&f->fmt.pix); vidioc_s_fmt_vid_out()
1152 f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height * bpp; vidioc_s_fmt_vid_out()
1155 vout->bpp = bpp; vidioc_s_fmt_vid_out()
1159 /* If YUYV then vrfb bpp is 2, for others its 1 */ vidioc_s_fmt_vid_out()
1886 vout->bpp = RGB565_BPP; omap_vout_setup_video_data()
/linux-4.4.14/drivers/gpu/drm/nouveau/
H A Dnouveau_display.h31 int crtc, bpp, pitch, x, y; member in struct:nouveau_page_flip_state
/linux-4.4.14/arch/powerpc/boot/
H A Dredboot.h43 short bpp; /* Bits/pixel */ member in struct:bd_info::__anon2229
/linux-4.4.14/arch/arm/mach-integrator/
H A Dimpd1.c98 .bpp = 16,
126 .bpp = 16,
155 .bpp = 16,
187 .bpp = 16,
/linux-4.4.14/drivers/gpu/drm/tegra/
H A Dfb.c148 unsigned int size, bpp; tegra_fb_create() local
156 bpp = drm_format_plane_cpp(cmd->pixel_format, i); tegra_fb_create()
159 width * bpp + cmd->offsets[i]; tegra_fb_create()
/linux-4.4.14/fs/xfs/
H A Dxfs_trans.h180 struct xfs_buf **bpp,
191 struct xfs_buf **bpp, xfs_trans_read_buf()
196 flags, bpp, ops); xfs_trans_read_buf()
184 xfs_trans_read_buf( struct xfs_mount *mp, struct xfs_trans *tp, struct xfs_buftarg *target, xfs_daddr_t blkno, int numblks, xfs_buf_flags_t flags, struct xfs_buf **bpp, const struct xfs_buf_ops *ops) xfs_trans_read_buf() argument
H A Dxfs_dquot.c410 struct xfs_buf **bpp) xfs_qm_dqrepair()
423 0, bpp, NULL); xfs_qm_dqrepair()
426 ASSERT(*bpp == NULL); xfs_qm_dqrepair()
429 (*bpp)->b_ops = &xfs_dquot_buf_ops; xfs_qm_dqrepair()
431 ASSERT(xfs_buf_islocked(*bpp)); xfs_qm_dqrepair()
432 d = (struct xfs_dqblk *)(*bpp)->b_addr; xfs_qm_dqrepair()
442 xfs_trans_brelse(tp, *bpp); xfs_qm_dqrepair()
453 * in the bpp param, and a ptr to the on-disk dquot within that buffer
929 struct xfs_buf **bpp) xfs_qm_dqflush()
941 *bpp = NULL; xfs_qm_dqflush()
1034 *bpp = bp; xfs_qm_dqflush()
405 xfs_qm_dqrepair( struct xfs_mount *mp, struct xfs_trans *tp, struct xfs_dquot *dqp, xfs_dqid_t firstid, struct xfs_buf **bpp) xfs_qm_dqrepair() argument
927 xfs_qm_dqflush( struct xfs_dquot *dqp, struct xfs_buf **bpp) xfs_qm_dqflush() argument
/linux-4.4.14/arch/sparc/include/uapi/asm/
H A Dfbio.h175 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
/linux-4.4.14/arch/m68k/include/asm/
H A Dfbio.h178 int mdi_mode; /* 8bpp, 16bpp or 32bpp */
H A Dmac_via.h268 static inline int rbv_set_video_bpp(int bpp) rbv_set_video_bpp() argument
270 char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1; rbv_set_video_bpp()
/linux-4.4.14/arch/arm/mach-s3c24xx/
H A Dmach-qt2410.c118 .bpp = 16,
140 .bpp = 16,
162 .bpp = 16,
H A Dmach-bast.c425 .bpp = 4,
443 .bpp = 8,
461 .bpp = 16,
/linux-4.4.14/fs/jfs/
H A Djfs_mount.c464 int readSuper(struct super_block *sb, struct buffer_head **bpp) readSuper() argument
467 *bpp = sb_bread(sb, SUPER1_OFF >> sb->s_blocksize_bits); readSuper()
468 if (*bpp) readSuper()
472 *bpp = sb_bread(sb, SUPER2_OFF >> sb->s_blocksize_bits); readSuper()
473 if (*bpp) readSuper()
/linux-4.4.14/drivers/media/pci/cobalt/
H A Dcobalt-v4l2.c99 s->width * s->bpp, s->stride, desc); cobalt_buf_init()
664 s->stride = timings->bt.width * s->bpp; cobalt_s_dv_timings()
832 s->bpp = COBALT_BYTES_PER_PIXEL_YUYV; cobalt_s_fmt_vid_cap()
835 s->bpp = COBALT_BYTES_PER_PIXEL_RGB24; cobalt_s_fmt_vid_cap()
838 s->bpp = COBALT_BYTES_PER_PIXEL_RGB32; cobalt_s_fmt_vid_cap()
947 s->bpp = COBALT_BYTES_PER_PIXEL_YUYV; cobalt_s_fmt_vid_out()
951 s->bpp = COBALT_BYTES_PER_PIXEL_RGB32; cobalt_s_fmt_vid_out()
1185 s->bpp = 1; cobalt_node_register()
1188 s->bpp = COBALT_BYTES_PER_PIXEL_RGB32; cobalt_node_register()
1191 s->bpp = COBALT_BYTES_PER_PIXEL_YUYV; cobalt_node_register()
1195 s->stride = s->width * s->bpp; cobalt_node_register()
/linux-4.4.14/net/sunrpc/
H A Dsvcauth_unix.c145 char **bpp, int *blen) ip_map_request()
155 qword_add(bpp, blen, im->m_class); ip_map_request()
156 qword_add(bpp, blen, text_addr); ip_map_request()
157 (*bpp)[-1] = '\n'; ip_map_request()
463 char **bpp, int *blen) unix_gid_request()
469 qword_add(bpp, blen, tuid); unix_gid_request()
470 (*bpp)[-1] = '\n'; unix_gid_request()
143 ip_map_request(struct cache_detail *cd, struct cache_head *h, char **bpp, int *blen) ip_map_request() argument
461 unix_gid_request(struct cache_detail *cd, struct cache_head *h, char **bpp, int *blen) unix_gid_request() argument
/linux-4.4.14/drivers/media/pci/ttpci/
H A Dav7110_hw.c876 int bpp; LoadBitmap() local
888 bpp=8; delta = 1; LoadBitmap()
890 bpp=4; delta = 2; LoadBitmap()
892 bpp=2; delta = 4; LoadBitmap()
894 bpp=1; delta = 8; LoadBitmap()
899 av7110->bmplen = ((dx * dy * bpp + 7) & ~7) / 8; LoadBitmap()
916 << ((delta - d - 1) * bpp)); LoadBitmap()
1010 uint w, h, bpp, bpl, size, lpb, bnum, brest; OSDSetBlock() local
1020 bpp = av7110->osdbpp[av7110->osdwin] + 1; OSDSetBlock()
1021 bpl = ((w * bpp + 7) & ~7) / 8; OSDSetBlock()
/linux-4.4.14/drivers/media/platform/
H A Dsh_vou.c146 unsigned char bpp; member in struct:sh_vou_fmt
157 .bpp = 12,
165 .bpp = 16,
173 .bpp = 24,
181 .bpp = 16,
189 .bpp = 16,
253 int bytes_per_line = vou_fmt[vou_dev->pix_idx].bpp * pix->width / 8; sh_vou_queue_setup()
269 unsigned bytes_per_line = vou_fmt[vou_dev->pix_idx].bpp * pix->width / 8; sh_vou_buf_prepare()
698 pix->sizeimage = pix->height * ((pix->width * vou_fmt[pix_idx].bpp) >> 3); sh_vou_try_fmt_vid_out()
865 ((vou_dev->pix.width * vou_fmt[vou_dev->pix_idx].bpp) >> 3); sh_vou_s_std()
/linux-4.4.14/drivers/dma/ipu/
H A Dipu_idmac.c200 u32 bpp:3; member in struct:chan_param_mem_planar
248 u32 bpp:3; member in struct:chan_param_mem_interleaved
300 params->pp.bpp = 3; ipu_ch_param_set_size()
307 params->pp.bpp = 0; ipu_ch_param_set_size()
313 params->ip.bpp = 2; ipu_ch_param_set_size()
326 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ ipu_ch_param_set_size()
339 params->ip.bpp = 1; /* 24 BPP & RGB PFS */ ipu_ch_param_set_size()
354 params->ip.bpp = 0; ipu_ch_param_set_size()
369 params->ip.bpp = 0; ipu_ch_param_set_size()
383 params->ip.bpp = 2; ipu_ch_param_set_size()
390 params->ip.bpp = 3; ipu_ch_param_set_size()
399 params->ip.bpp = 3; ipu_ch_param_set_size()
408 params->ip.bpp = 3; ipu_ch_param_set_size()
/linux-4.4.14/drivers/gpu/drm/vmwgfx/
H A Dvmwgfx_fb.c94 DRM_ERROR("Bad depth %u, bpp %u.\n", par->set_fb->depth, vmw_fb_setcolreg()
114 DRM_ERROR("Bad bpp %u.\n", var->bits_per_pixel); vmw_fb_check_var()
413 DRM_ERROR("Bad bpp %u.\n", var->bits_per_pixel); vmw_fb_compute_depth()
482 mode_cmd.bpp = var->bits_per_pixel; vmw_fb_kms_framebuffer()
483 mode_cmd.pitch = ((mode_cmd.bpp + 7) / 8) * mode_cmd.width; vmw_fb_kms_framebuffer()
488 cur_fb->bits_per_pixel == mode_cmd.bpp && vmw_fb_kms_framebuffer()
H A Dvmwgfx_kms.c585 vfbs->base.base.bits_per_pixel = mode_cmd->bpp; vmw_kms_new_framebuffer_surface()
851 /* Only support 32 bpp for 32 and 24 depth fbs */ vmw_kms_new_framebuffer_dmabuf()
852 if (mode_cmd->bpp == 32) vmw_kms_new_framebuffer_dmabuf()
856 mode_cmd->depth, mode_cmd->bpp); vmw_kms_new_framebuffer_dmabuf()
860 /* Only support 16 bpp for 16 and 15 depth fbs */ vmw_kms_new_framebuffer_dmabuf()
861 if (mode_cmd->bpp == 16) vmw_kms_new_framebuffer_dmabuf()
865 mode_cmd->depth, mode_cmd->bpp); vmw_kms_new_framebuffer_dmabuf()
879 vfbd->base.base.bits_per_pixel = mode_cmd->bpp; vmw_kms_new_framebuffer_dmabuf()
991 &mode_cmd.bpp); vmw_kms_fb_create()
1195 unsigned bpp, unsigned depth) vmw_kms_write_svga()
1204 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); vmw_kms_write_svga()
1207 DRM_ERROR("Invalid depth %u for %u bpp, host expects %u\n", vmw_kms_write_svga()
1208 depth, bpp, vmw_read(vmw_priv, SVGA_REG_DEPTH)); vmw_kms_write_svga()
1544 * If using screen objects, then assume 32-bpp because that's what the vmw_du_connector_fill_modes()
1675 * 1. Bounding box (assuming 32bpp) must be < prim_bb_mem vmw_kms_update_layout_ioctl()
1676 * 2. Total pixels (assuming 32bpp) must be < prim_bb_mem vmw_kms_update_layout_ioctl()
1193 vmw_kms_write_svga(struct vmw_private *vmw_priv, unsigned width, unsigned height, unsigned pitch, unsigned bpp, unsigned depth) vmw_kms_write_svga() argument
/linux-4.4.14/drivers/media/platform/xilinx/
H A Dxilinx-dma.c366 dma->sgl[0].size = dma->format.width * dma->fmtinfo->bpp; xvip_dma_buffer_queue()
568 align = lcm(dma->align, info->bpp); __xvip_dma_try_format()
571 width = rounddown(pix->width * info->bpp, align); __xvip_dma_try_format()
573 pix->width = clamp(width, min_width, max_width) / info->bpp; __xvip_dma_try_format()
581 min_bpl = pix->width * info->bpp; __xvip_dma_try_format()
675 dma->format.bytesperline = dma->format.width * dma->fmtinfo->bpp; xvip_dma_init()
/linux-4.4.14/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c1661 u32 h, u32 color, u32 pitch, u32 bpp, u32 rop) intelfbhw_do_fillrect()
1666 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, " intelfbhw_do_fillrect()
1667 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop); intelfbhw_do_fillrect()
1671 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8)); intelfbhw_do_fillrect()
1673 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT); intelfbhw_do_fillrect()
1676 switch (bpp) { intelfbhw_do_fillrect()
1706 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp) intelfbhw_do_bitblt()
1711 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n", intelfbhw_do_bitblt()
1712 curx, cury, dstx, dsty, w, h, pitch, bpp); intelfbhw_do_bitblt()
1725 switch (bpp) { intelfbhw_do_bitblt()
1752 u32 bpp) intelfbhw_do_drawglyph()
1794 switch (bpp) { intelfbhw_do_drawglyph()
1660 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h, u32 color, u32 pitch, u32 bpp, u32 rop) intelfbhw_do_fillrect() argument
1705 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury, u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp) intelfbhw_do_bitblt() argument
1750 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w, u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp) intelfbhw_do_drawglyph() argument
/linux-4.4.14/drivers/gpu/drm/omapdrm/
H A Domap_fb.c42 /* 16bpp [A]RGB: */
50 /* 24bpp RGB: */
52 /* 32bpp [A]RGB: */
/linux-4.4.14/fs/nfs/
H A Ddns_resolve.c132 char **bpp, int *blen) nfs_dns_request()
136 qword_add(bpp, blen, key->hostname); nfs_dns_request()
137 (*bpp)[-1] = '\n'; nfs_dns_request()
130 nfs_dns_request(struct cache_detail *cd, struct cache_head *ch, char **bpp, int *blen) nfs_dns_request() argument

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