| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | uvd_v1_0.c | 226 WREG32_P(UVD_VCPU_CNTL, 0x10, ~0x10); in uvd_v1_0_init()
276 WREG32_P(UVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v1_0_start()
279 WREG32_P(UVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v1_0_start()
280 WREG32_P(UVD_RB_ARB_CTRL, 1 << 3, ~(1 << 3)); in uvd_v1_0_start()
290 WREG32_P(SRBM_SOFT_RESET, 0, ~SOFT_RESET_UVD); in uvd_v1_0_start()
320 WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v1_0_start()
322 WREG32_P(UVD_RB_ARB_CTRL, 0, ~(1 << 3)); in uvd_v1_0_start()
341 WREG32_P(UVD_SOFT_RESET, VCPU_SOFT_RESET, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
343 WREG32_P(UVD_SOFT_RESET, 0, ~VCPU_SOFT_RESET); in uvd_v1_0_start()
354 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v1_0_start()
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| D | rs780_dpm.c | 201 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, RANGE_SLOW_CLK_FEEDBACK_DIV_EN, in rs780_preset_ranges_slow_clk_fbdiv_en()
204 WREG32_P(FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1, in rs780_preset_ranges_slow_clk_fbdiv_en()
213 WREG32_P(FVTHROT_FBDIV_REG1, STARTING_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
216 WREG32_P(FVTHROT_FBDIV_REG2, FORCED_FEEDBACK_DIV(fbdiv), in rs780_preset_starting_fbdiv()
219 WREG32_P(FVTHROT_FBDIV_REG1, FORCE_FEEDBACK_DIV, ~FORCE_FEEDBACK_DIV); in rs780_preset_starting_fbdiv()
260 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
264 WREG32_P(FVTHROT_PWM_CTRL_REG0, in rs780_voltage_scaling_init()
268 WREG32_P(FVTHROT_PWM_CTRL_REG0, FORCE_STARTING_PWM_HIGHTIME, in rs780_voltage_scaling_init()
272 WREG32_P(FVTHROT_PWM_CTRL_REG0, INVERT_PWM_WAVEFORM, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init()
274 WREG32_P(FVTHROT_PWM_CTRL_REG0, 0, ~INVERT_PWM_WAVEFORM); in rs780_voltage_scaling_init()
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| D | r600_dpm.c | 244 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
246 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in r600_gfx_clockgating_enable()
266 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
268 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in r600_dynamicpm_enable()
274 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
276 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in r600_enable_thermal_protection()
281 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in r600_enable_acpi_pm()
287 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
289 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in r600_enable_dynamic_pcie_gen2()
303 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in r600_enable_sclk_control()
[all …]
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| D | vce_v1_0.c | 222 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v1_0_resume()
223 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v1_0_resume()
224 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v1_0_resume()
227 WREG32_P(VCE_LMI_FW_PERIODIC_CTRL, 0x4, ~0x4); in vce_v1_0_resume()
230 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v1_0_resume()
252 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v1_0_resume()
295 WREG32_P(VCE_STATUS, 1, ~1); in vce_v1_0_start()
311 WREG32_P(VCE_VCPU_CNTL, VCE_CLK_EN, ~VCE_CLK_EN); in vce_v1_0_start()
313 WREG32_P(VCE_SOFT_RESET, in vce_v1_0_start()
321 WREG32_P(VCE_SOFT_RESET, 0, ~( in vce_v1_0_start()
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| D | vce_v2_0.c | 158 WREG32_P(VCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_resume()
159 WREG32_P(VCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_resume()
160 WREG32_P(VCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_resume()
164 WREG32_P(VCE_LMI_CACHE_CTRL, 0x0, ~0x1); in vce_v2_0_resume()
186 WREG32_P(VCE_LMI_CTRL2, 0x0, ~0x100); in vce_v2_0_resume()
188 WREG32_P(VCE_SYS_INT_EN, VCE_SYS_INT_TRAP_INTERRUPT_EN, in vce_v2_0_resume()
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| D | r600_hdmi.c | 186 WREG32_P(acr_ctl + offset, in r600_hdmi_update_acr()
192 WREG32_P(HDMI0_ACR_32_0 + offset, in r600_hdmi_update_acr()
195 WREG32_P(HDMI0_ACR_32_1 + offset, in r600_hdmi_update_acr()
199 WREG32_P(HDMI0_ACR_44_0 + offset, in r600_hdmi_update_acr()
202 WREG32_P(HDMI0_ACR_44_1 + offset, in r600_hdmi_update_acr()
206 WREG32_P(HDMI0_ACR_48_0 + offset, in r600_hdmi_update_acr()
209 WREG32_P(HDMI0_ACR_48_1 + offset, in r600_hdmi_update_acr()
310 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_hdmi_audio_workaround()
356 WREG32_P(HDMI0_AUDIO_PACKET_CONTROL + offset, in r600_set_audio_packet()
370 WREG32_P(HDMI0_INFOFRAME_CONTROL1 + offset, in r600_set_audio_packet()
[all …]
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| D | sumo_dpm.c | 92 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
94 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in sumo_gfx_clockgating_enable()
95 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
96 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in sumo_gfx_clockgating_enable()
129 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK); in sumo_program_git()
176 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
182 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u), in sumo_gfx_powergating_initialize()
278 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable()
280 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN); in sumo_gfx_powergating_enable()
437 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK); in sumo_program_tp()
[all …]
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| D | dce3_1_afmt.c | 180 WREG32_P(HDMI0_ACR_32_0 + offset, in dce3_2_hdmi_update_acr()
183 WREG32_P(HDMI0_ACR_32_1 + offset, in dce3_2_hdmi_update_acr()
187 WREG32_P(HDMI0_ACR_44_0 + offset, in dce3_2_hdmi_update_acr()
190 WREG32_P(HDMI0_ACR_44_1 + offset, in dce3_2_hdmi_update_acr()
194 WREG32_P(HDMI0_ACR_48_0 + offset, in dce3_2_hdmi_update_acr()
197 WREG32_P(HDMI0_ACR_48_1 + offset, in dce3_2_hdmi_update_acr()
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| D | rv6xx_dpm.c | 318 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_s()
325 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_set_engine_spread_spectrum_clk_v()
333 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
336 WREG32_P(CG_SPLL_SPREAD_SPECTRUM_LOW + (index * 4), in rv6xx_enable_engine_spread_spectrum()
343 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKS(clk_s), ~CLKS_MASK); in rv6xx_set_memory_spread_spectrum_clk_s()
349 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, CLKV(clk_v), ~CLKV_MASK); in rv6xx_set_memory_spread_spectrum_clk_v()
356 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, SSEN, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
358 WREG32_P(CG_MPLL_SPREAD_SPECTRUM, 0, ~SSEN); in rv6xx_enable_memory_spread_spectrum()
365 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
367 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); in rv6xx_enable_dynamic_spread_spectrum()
[all …]
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| D | rv770_dpm.c | 134 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
136 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in rv770_gfx_clock_gating_enable()
137 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
138 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in rv770_gfx_clock_gating_enable()
177 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in rv770_restore_cgcg()
182 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv770_start_dpm()
184 WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv770_start_dpm()
186 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv770_start_dpm()
198 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv770_stop_dpm()
200 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv770_stop_dpm()
[all …]
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| D | cypress_dpm.c | 92 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
94 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in cypress_enable_dynamic_pcie_gen2()
103 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
104 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
105 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
110 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
141 WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN); in cypress_gfx_clock_gating_enable()
143 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
145 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in cypress_gfx_clock_gating_enable()
146 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in cypress_gfx_clock_gating_enable()
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| D | rv770_smc.c | 394 WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); in rv770_start_smc()
399 WREG32_P(SMC_IO, 0, ~SMC_RST_N); in rv770_reset_smc()
404 WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); in rv770_stop_smc_clock()
409 WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); in rv770_start_smc_clock()
433 WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); in rv770_send_msg_to_smc()
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| D | ci_smc.c | 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_set_smc_sram_address()
251 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
261 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in ci_load_smc_ucode()
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| D | rv770.c | 57 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
63 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in rv770_set_uvd_clocks()
78 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); in rv770_set_uvd_clocks()
81 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK)); in rv770_set_uvd_clocks()
84 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in rv770_set_uvd_clocks()
85 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1)); in rv770_set_uvd_clocks()
92 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in rv770_set_uvd_clocks()
95 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK); in rv770_set_uvd_clocks()
96 WREG32_P(CG_UPLL_FUNC_CNTL_2, in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
[all …]
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| D | si_smc.c | 42 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_set_smc_sram_address()
266 WREG32_P(SMC_IND_ACCESS_CNTL, AUTO_INCREMENT_IND_0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
276 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in si_load_smc_ucode()
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| D | radeon_legacy_crtc.c | 327 WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
329 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
331 WREG32_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
341 WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask)); in radeon_crtc_dpms()
343 WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN | in radeon_crtc_dpms()
345 WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~(mask | crtc_ext_cntl)); in radeon_crtc_dpms()
937 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
958 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
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| D | rv730_dpm.c | 453 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in rv730_start_dpm()
455 WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); in rv730_start_dpm()
457 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in rv730_start_dpm()
469 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in rv730_stop_dpm()
471 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in rv730_stop_dpm()
473 WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); in rv730_stop_dpm()
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| D | trinity_dpm.c | 388 WREG32_P(CG_GIPOTS, CG_GIPOT(p), ~CG_GIPOT_MASK); in trinity_gfx_powergating_initialize()
445 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
447 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN); in trinity_gfx_clockgating_enable()
448 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable()
449 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON); in trinity_gfx_clockgating_enable()
460 WREG32_P(seq[i], seq[i+1], ~seq[i+2]); in trinity_program_clk_gating_hw_sequence()
508 WREG32_P(SCLK_PWRMGT_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable()
510 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_PWR_DOWN_EN); in trinity_gfx_powergating_enable()
761 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in trinity_start_dpm()
762 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~EN); in trinity_start_dpm()
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| D | kv_smc.c | 84 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0); in kv_set_smc_sram_address()
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| D | si_dpm.c | 3318 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); in si_set_dpm_event_sources()
3320 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_set_dpm_event_sources()
3322 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in si_set_dpm_event_sources()
3347 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); in si_start_dpm()
3352 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in si_stop_dpm()
3358 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3360 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); in si_enable_sclk_control()
3605 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); in si_enable_thermal_protection()
3607 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); in si_enable_thermal_protection()
3612 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); in si_enable_acpi_power_management()
[all …]
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| D | rv740_dpm.c | 401 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); in rv740_enable_mclk_spread_spectrum()
403 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); in rv740_enable_mclk_spread_spectrum()
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| D | evergreen.c | 1148 WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK)); in sumo_set_uvd_clock()
1191 WREG32_P(CG_UPLL_FUNC_CNTL_2, in evergreen_set_uvd_clocks()
1196 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in evergreen_set_uvd_clocks()
1200 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1211 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in evergreen_set_uvd_clocks()
1214 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1215 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in evergreen_set_uvd_clocks()
1218 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1227 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in evergreen_set_uvd_clocks()
1230 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in evergreen_set_uvd_clocks()
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| D | radeon_uvd.c | 979 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
984 WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
995 WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); in radeon_uvd_send_upll_ctlreq()
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| D | radeon_legacy_encoders.c | 615 WREG32_P(RADEON_DAC_CNTL, in radeon_legacy_primary_dac_mode_set()
1279 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in radeon_legacy_tv_dac_mode_set()
1316 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); in r300_legacy_tv_detect()
1366 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in r300_legacy_tv_detect()
1607 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); in radeon_legacy_tv_dac_detect()
1663 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); in radeon_legacy_tv_dac_detect()
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| D | btc_dpm.c | 1381 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE); in btc_enable_dynamic_pcie_gen2()
1383 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); in btc_enable_dynamic_pcie_gen2()
1669 WREG32_P(SCLK_PSKIP_CNTL, PSKIP_ON_ALLOW_STOP_HI(32), in btc_init_smc_table()
1776 WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); in btc_set_arb0_registers()
1780 WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); in btc_set_arb0_registers()
1821 WREG32_P(MC_ARB_RFSH_RATE, POWERMODE0(val), ~POWERMODE0_MASK); in btc_set_ulv_dram_timing()
1824 WREG32_P(MC_ARB_BURST_TIME, STATE0(val), ~STATE0_MASK); in btc_set_ulv_dram_timing()
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| D | si.c | 6787 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); in si_irq_process()
7328 WREG32_P(CG_UPLL_FUNC_CNTL_2, in si_set_uvd_clocks()
7333 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); in si_set_uvd_clocks()
7347 WREG32_P(CG_UPLL_FUNC_CNTL_5, 0, ~RESET_ANTI_MUX_MASK); in si_set_uvd_clocks()
7350 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK); in si_set_uvd_clocks()
7353 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK); in si_set_uvd_clocks()
7356 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7365 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in si_set_uvd_clocks()
7368 WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK); in si_set_uvd_clocks()
7371 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
[all …]
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| D | r600.c | 203 WREG32_P(CG_UPLL_FUNC_CNTL_2, in r600_set_uvd_clocks()
208 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~( in r600_set_uvd_clocks()
212 WREG32_P(GFX_MACRO_BYPASS_CNTL, UPLL_BYPASS_CNTL, in r600_set_uvd_clocks()
217 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); in r600_set_uvd_clocks()
242 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
246 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REFCLK_SRC_SEL_MASK, in r600_set_uvd_clocks()
250 WREG32_P(CG_UPLL_FUNC_CNTL, in r600_set_uvd_clocks()
254 WREG32_P(CG_UPLL_FUNC_CNTL_2, in r600_set_uvd_clocks()
266 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); in r600_set_uvd_clocks()
271 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK); in r600_set_uvd_clocks()
[all …]
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| D | ni_dpm.c | 1021 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); in ni_stop_dpm()
1205 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1206 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1207 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1211 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
1541 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK); in ni_copy_and_switch_arb_sets()
1546 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK); in ni_copy_and_switch_arb_sets()
1551 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK); in ni_copy_and_switch_arb_sets()
1556 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK); in ni_copy_and_switch_arb_sets()
1564 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK); in ni_copy_and_switch_arb_sets()
[all …]
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| D | radeon_cursor.c | 133 WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN | in radeon_show_cursor()
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| D | evergreen_hdmi.c | 222 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset, in evergreen_set_avi_packet()
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| D | ni.c | 1722 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA); in cayman_cp_resume()
1729 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA); in cayman_cp_resume()
2650 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK)); in tn_set_vce_clocks()
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| D | radeon.h | 2555 #define WREG32_P(reg, val, mask) \ macro
2562 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2563 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
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| D | atombios_crtc.c | 1391 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1599 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
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| D | radeon_display.c | 71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); in avivo_crtc_load_lut()
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| D | ci_dpm.c | 1488 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN); in ci_enable_sclk_mclk_dpm()
1534 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN); in ci_start_dpm()
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| D | r100.c | 2748 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, in r100_get_accessible_vram()
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| D | cik.c | 8279 WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1); in cik_irq_process()
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | vce_v3_0.c | 125 WREG32_P(mmGRBM_GFX_INDEX, 0, in vce_v3_0_start()
128 WREG32_P(mmGRBM_GFX_INDEX, in vce_v3_0_start()
135 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v3_0_start()
137 WREG32_P(mmVCE_VCPU_CNTL, 1, ~0x200001); in vce_v3_0_start()
139 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, in vce_v3_0_start()
142 WREG32_P(mmVCE_SOFT_RESET, in vce_v3_0_start()
148 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v3_0_start()
164 WREG32_P(mmVCE_SOFT_RESET, in vce_v3_0_start()
168 WREG32_P(mmVCE_SOFT_RESET, 0, in vce_v3_0_start()
175 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v3_0_start()
[all …]
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| D | vce_v2_0.c | 114 WREG32_P(mmVCE_STATUS, 1, ~1); in vce_v2_0_start()
130 WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK); in vce_v2_0_start()
132 WREG32_P(mmVCE_SOFT_RESET, in vce_v2_0_start()
138 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); in vce_v2_0_start()
153 WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK, in vce_v2_0_start()
156 WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK); in vce_v2_0_start()
162 WREG32_P(mmVCE_STATUS, 0, ~1); in vce_v2_0_start()
417 WREG32_P(mmVCE_CLOCK_GATING_A, 0, ~(1 << 16)); in vce_v2_0_mc_resume()
418 WREG32_P(mmVCE_UENC_CLOCK_GATING, 0x1FF000, ~0xFF9FF000); in vce_v2_0_mc_resume()
419 WREG32_P(mmVCE_UENC_REG_CLOCK_GATING, 0x3F, ~0x3F); in vce_v2_0_mc_resume()
[all …]
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| D | uvd_v6_0.c | 298 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v6_0_start()
310 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v6_0_start()
313 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v6_0_start()
325 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v6_0_start()
355 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v6_0_start()
375 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v6_0_start()
378 WREG32_P(mmUVD_SOFT_RESET, 0, in uvd_v6_0_start()
389 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v6_0_start()
392 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v6_0_start()
423 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v6_0_start()
[all …]
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| D | uvd_v5_0.c | 300 WREG32_P(mmUVD_POWER_STATUS, 0, ~(1 << 2)); in uvd_v5_0_start()
312 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v5_0_start()
315 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v5_0_start()
327 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v5_0_start()
357 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v5_0_start()
376 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v5_0_start()
379 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v5_0_start()
389 WREG32_P(mmUVD_MASTINT_EN, 3 << 1, ~(3 << 1)); in uvd_v5_0_start()
392 WREG32_P(mmUVD_STATUS, 0, ~(2 << 1)); in uvd_v5_0_start()
423 WREG32_P(mmUVD_RBC_RB_CNTL, 0, ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK); in uvd_v5_0_start()
[all …]
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| D | uvd_v4_2.c | 277 WREG32_P(mmUVD_MASTINT_EN, 0, ~(1 << 1)); in uvd_v4_2_start()
280 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_start()
292 WREG32_P(mmSRBM_SOFT_RESET, 0, ~SRBM_SOFT_RESET__SOFT_RESET_UVD_MASK); in uvd_v4_2_start()
322 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_start()
341 WREG32_P(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK, in uvd_v4_2_start()
344 WREG32_P(mmUVD_SOFT_RESET, 0, ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK); in uvd_v4_2_start()
355 WREG32_P(mmUVD_MASTINT_EN, 3<<1, ~(3 << 1)); in uvd_v4_2_start()
379 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v4_2_start()
397 WREG32_P(mmUVD_LMI_CTRL2, 1 << 8, ~(1 << 8)); in uvd_v4_2_stop()
408 WREG32_P(mmUVD_LMI_CTRL2, 0, ~(1 << 8)); in uvd_v4_2_stop()
[all …]
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| D | ci_smc.c | 45 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); in ci_set_smc_sram_address()
234 WREG32_P(mmSMC_IND_ACCESS_CNTL, SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK, in amdgpu_ci_load_smc_ucode()
245 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, ~SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK); in amdgpu_ci_load_smc_ucode()
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| D | kv_smc.c | 87 WREG32_P(mmSMC_IND_ACCESS_CNTL, 0, in kv_set_smc_sram_address()
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| D | amdgpu.h | 2158 #define WREG32_P(reg, val, mask) \ macro
2165 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
2166 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
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| D | gmc_v8_0.c | 1287 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); in gmc_v8_0_process_interrupt()
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| D | gmc_v7_0.c | 1327 WREG32_P(mmVM_CONTEXT1_CNTL2, 1, ~1); in gmc_v7_0_process_interrupt()
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| D | ci_dpm.c | 223 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE0__SHIFT), in ci_copy_and_switch_arb_sets()
229 WREG32_P(mmMC_ARB_BURST_TIME, (burst_time << MC_ARB_BURST_TIME__STATE1__SHIFT), in ci_copy_and_switch_arb_sets()
238 WREG32_P(mmMC_ARB_CG, (arb_freq_dest) << MC_ARB_CG__CG_ARB_REQ__SHIFT, in ci_copy_and_switch_arb_sets()
1615 WREG32_P(mmMC_SEQ_CNTL_3, MC_SEQ_CNTL_3__CAC_EN_MASK, in ci_enable_sclk_mclk_dpm()
1662 WREG32_P(mmBIF_LNCNT_RESET, 0, ~BIF_LNCNT_RESET__RESET_LNCNT_EN_MASK); in ci_start_dpm()
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| D | dce_v8_0.c | 1869 WREG32_P(mmHDMI_INFOFRAME_CONTROL1 + offset, in dce_v8_0_afmt_setmode()
2144 WREG32_P(mmGRPH_LUT_10BIT_BYPASS_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_crtc_do_set_base()
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