Searched refs:WREG32_MC (Results 1 - 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Drs400.c65 WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); rs400_gart_tlb_flush()
73 WREG32_MC(RS480_GART_CACHE_CNTRL, 0); rs400_gart_tlb_flush()
114 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); rs400_gart_enable()
143 WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); rs400_gart_enable()
144 WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); rs400_gart_enable()
152 WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); rs400_gart_enable()
164 WREG32_MC(RS480_GART_BASE, tmp); rs400_gart_enable()
166 WREG32_MC(RS480_GART_FEATURE_ID, rs400_gart_enable()
170 WREG32_MC(RS480_AGP_MODE_CNTL, rs400_gart_enable()
178 WREG32_MC(RS480_MC_MISC_CNTL, tmp); rs400_gart_enable()
182 WREG32_MC(RS480_MC_MISC_CNTL, tmp); rs400_gart_enable()
185 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); rs400_gart_enable()
200 WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); rs400_gart_disable()
201 WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); rs400_gart_disable()
H A Dr520.c147 WREG32_MC(R_000004_MC_FB_LOCATION, r520_mc_program()
153 WREG32_MC(R_000005_MC_AGP_LOCATION, r520_mc_program()
156 WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); r520_mc_program()
157 WREG32_MC(R_000007_AGP_BASE_2, r520_mc_program()
160 WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); r520_mc_program()
161 WREG32_MC(R_000006_AGP_BASE, 0); r520_mc_program()
162 WREG32_MC(R_000007_AGP_BASE_2, 0); r520_mc_program()
H A Drs600.c518 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush()
522 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush()
526 WREG32_MC(R_000100_MC_PT0_CNTL, tmp); rs600_gart_tlb_flush()
563 WREG32_MC(R_000100_MC_PT0_CNTL, rs600_gart_enable()
568 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i, rs600_gart_enable()
579 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL, rs600_gart_enable()
585 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0); rs600_gart_enable()
588 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR, rs600_gart_enable()
590 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); rs600_gart_enable()
591 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); rs600_gart_enable()
592 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0); rs600_gart_enable()
595 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); rs600_gart_enable()
596 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); rs600_gart_enable()
600 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1))); rs600_gart_enable()
602 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1))); rs600_gart_enable()
616 WREG32_MC(R_000100_MC_PT0_CNTL, 0); rs600_gart_disable()
618 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES); rs600_gart_disable()
963 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF); rs600_mc_program()
964 WREG32_MC(R_000006_AGP_BASE, 0); rs600_mc_program()
965 WREG32_MC(R_000007_AGP_BASE_2, 0); rs600_mc_program()
967 WREG32_MC(R_000004_MC_FB_LOCATION, rs600_mc_program()
H A Drv515.c481 WREG32_MC(R_000001_MC_FB_LOCATION, rv515_mc_program()
487 WREG32_MC(R_000002_MC_AGP_LOCATION, rv515_mc_program()
490 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); rv515_mc_program()
491 WREG32_MC(R_000004_MC_AGP_BASE_2, rv515_mc_program()
494 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF); rv515_mc_program()
495 WREG32_MC(R_000003_MC_AGP_BASE, 0); rv515_mc_program()
496 WREG32_MC(R_000004_MC_AGP_BASE_2, 0); rv515_mc_program()
1303 WREG32_MC(MC_MISC_LAT_TIMER, tmp); rv515_bandwidth_update()
H A Drs690.c616 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp); rs690_bandwidth_update()
686 WREG32_MC(R_000100_MCCFG_FB_LOCATION, rs690_mc_program()
H A Dradeon.h2536 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) macro

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