Searched refs:UART_CR (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/arch/arm/mach-netx/include/mach/
H A Duncompress.h36 #define UART_CR 0x14 macro
47 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) putc()
49 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) putc()
62 if (REG(UART1_BASE + UART_CR) & CR_UART_EN) flush()
64 else if (REG(UART2_BASE + UART_CR) & CR_UART_EN) flush()
/linux-4.4.14/drivers/tty/serial/
H A Dnetx-serial.c49 UART_CR = 0x14, enumerator in enum:uart_regs
121 val = readl(port->membase + UART_CR); netx_stop_tx()
122 writel(val & ~CR_TIE, port->membase + UART_CR); netx_stop_tx()
128 val = readl(port->membase + UART_CR); netx_stop_rx()
129 writel(val & ~CR_RIE, port->membase + UART_CR); netx_stop_rx()
135 val = readl(port->membase + UART_CR); netx_enable_ms()
136 writel(val | CR_MSIE, port->membase + UART_CR); netx_enable_ms()
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR); netx_start_tx()
323 port->membase + UART_CR); netx_startup()
331 writel(0, port->membase + UART_CR) ; netx_shutdown()
382 old_cr = readl(port->membase + UART_CR); netx_set_termios()
386 port->membase + UART_CR); netx_set_termios()
392 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR); netx_set_termios()
427 writel(old_cr, port->membase + UART_CR); netx_set_termios()
541 cr_save = readl(port->membase + UART_CR); netx_console_write()
542 writel(cr_save | CR_UART_EN, port->membase + UART_CR); netx_console_write()
547 writel(cr_save, port->membase + UART_CR); netx_console_write()
616 if (readl(sport->port.membase + UART_CR) & CR_UART_EN) { netx_console_setup()
H A Dmsm_serial.c230 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); msm_wait_for_xmitr()
288 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); msm_complete_tx_dma()
289 msm_write(port, UART_CR_TX_ENABLE, UART_CR); msm_complete_tx_dma()
398 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); msm_complete_rx_dma()
486 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_start_rx_dma()
487 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); msm_start_rx_dma()
535 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); msm_handle_rx_dm()
592 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_handle_rx_dm()
594 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); msm_handle_rx_dm()
612 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); msm_handle_rx()
755 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); msm_handle_delta_cts()
775 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); msm_uart_irq()
781 msm_write(port, val, UART_CR); msm_uart_irq()
783 msm_write(port, val, UART_CR); msm_uart_irq()
821 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); msm_reset()
822 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); msm_reset()
823 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); msm_reset()
824 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); msm_reset()
825 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); msm_reset()
826 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); msm_reset()
842 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); msm_set_mctrl()
852 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); msm_break_ctl()
854 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); msm_break_ctl()
941 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); msm_set_baud_rate()
945 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); msm_set_baud_rate()
954 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_set_baud_rate()
956 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); msm_set_baud_rate()
1234 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); msm_poll_get_char_dm()
1238 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); msm_poll_get_char_dm()
1241 UART_CR); msm_poll_get_char_dm()
H A Dmsm_serial.h47 #define UART_CR 0x0010 macro

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