Searched refs:TXIENB (Results 1 – 1 of 1) sorted by relevance
63 #define TXIENB 0x40 /* Transmit Interrupt Enable */ macro92 #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB)94 #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB)96 #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB)98 #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB)300 if ((status & TXIENB) && (status & TXEMPTY)) { in arc_serial_isr()