Searched refs:SA5_REPLY_INTR_MASK_OFFSET (Results 1 – 3 of 3) sorted by relevance
166 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 macro243 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()244 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()249 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()250 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()263 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()264 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()269 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()270 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5B_intr_mask()279 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()[all …]
363 #define SA5_REPLY_INTR_MASK_OFFSET 0x34 macro436 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()437 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()441 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()442 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_intr_mask()450 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()451 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()455 h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()456 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); in SA5_performant_intr_mask()
7805 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); in hpsa_init_reset_devices()