Lines Matching refs:SA5_REPLY_INTR_MASK_OFFSET

166 #define SA5_REPLY_INTR_MASK_OFFSET	0x34  macro
243 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
244 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
249 			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
250 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_intr_mask()
263                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
264 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
269                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
270 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5B_intr_mask()
279 		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
280 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
284 				h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()
285 		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);  in SA5_performant_intr_mask()