| /linux-4.4.14/arch/arm/mach-imx/ |
| D | anatop.c | 21 #define REG_SET 0x4 macro
53 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
59 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
65 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
71 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
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| /linux-4.4.14/drivers/thermal/ |
| D | imx_thermal.c | 28 #define REG_SET 0x4 macro
116 regmap_write(map, TEMPSENSE2 + REG_SET, critical_value << in imx_set_panic_temp()
129 regmap_write(map, TEMPSENSE0 + REG_SET, alarm_value << in imx_set_alarm_temp()
152 regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP); in imx_get_temp()
168 regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); in imx_get_temp()
229 regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP); in imx_set_mode()
237 regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); in imx_set_mode()
503 regmap_write(map, TEMPSENSE2 + REG_SET, in imx_thermal_probe()
523 regmap_write(map, MISC0 + REG_SET, MISC0_REFTOP_SELBIASOFF); in imx_thermal_probe()
524 regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); in imx_thermal_probe()
[all …]
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | r300d.h | 61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
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| D | rv515d.h | 201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
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| D | r100d.h | 60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
61 REG_SET(PACKET0_COUNT, (n)))
62 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n)))
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| D | rs400.c | 149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
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| D | r100.c | 1168 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
1169 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | in r100_cp_init()
1170 REG_SET(RADEON_MAX_FETCH, max_fetch)); in r100_cp_init()
1201 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | in r100_cp_init()
1202 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); in r100_cp_init()
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| D | nid.h | 1154 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | sid.h | 1591 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | cikd.h | 1691 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | evergreend.h | 1540 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | r600d.h | 34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | radeon.h | 2531 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
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| /linux-4.4.14/drivers/video/fbdev/ |
| D | mxsfb.c | 55 #define REG_SET 4 macro
356 writel(CTRL_DOTCLK_MODE, host->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
363 writel(CTRL_RUN, host->base + LCDC_CTRL + REG_SET); in mxsfb_enable_controller()
438 writel(CTRL1_FIFO_CLEAR, host->base + LCDC_CTRL1 + REG_SET); in mxsfb_set_par()
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | vid.h | 104 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | cikd.h | 218 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
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| D | amdgpu.h | 2146 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
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| /linux-4.4.14/drivers/gpu/drm/rockchip/ |
| D | rockchip_drm_vop.c | 48 #define REG_SET(x, base, reg, v, mode) \ macro
52 REG_SET(x, win->base, win->phy->name, v, RELAXED)
54 REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
56 REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
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