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Searched refs:RADEON_CP_RB_CNTL (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Drs600.c463 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset()
464 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset()
467 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()
Dr300.c428 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
429 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r300_asic_reset()
432 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()
Dradeon_cp.c810 RADEON_WRITE(RADEON_CP_RB_CNTL, in radeon_cp_init_ring_buffer()
816 RADEON_WRITE(RADEON_CP_RB_CNTL, in radeon_cp_init_ring_buffer()
902 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) | in radeon_test_writeback()
Dr100.c1174 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); in r100_cp_init()
1180 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); in r100_cp_init()
1197 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init()
2573 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset()
2574 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA); in r100_asic_reset()
2577 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset()
4008 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity()
4010 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
Dradeon_drv.h1033 #define RADEON_CP_RB_CNTL 0x0704 macro
Dradeon_reg.h3297 #define RADEON_CP_RB_CNTL 0x0704 macro