Searched refs:RADEON_CP_CSQ_CNTL (Results 1 – 6 of 6) sorted by relevance
1205 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); in r100_cp_init()1248 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_cp_disable()2572 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_asic_reset()4004 tmp = RREG32(RADEON_CP_CSQ_CNTL); in r100_restore_sanity()4006 WREG32(RADEON_CP_CSQ_CNTL, 0); in r100_restore_sanity()
610 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode); in radeon_do_cp_start()676 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS); in radeon_do_cp_stop()
462 WREG32(RADEON_CP_CSQ_CNTL, 0); in rs600_asic_reset()
427 WREG32(RADEON_CP_CSQ_CNTL, 0); in r300_asic_reset()
1047 #define RADEON_CP_CSQ_CNTL 0x0740 macro
3333 #define RADEON_CP_CSQ_CNTL 0x0740 macro