Searched refs:RADEON_AIC_CNTL (Results 1 – 4 of 4) sorted by relevance
657 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_enable()658 WREG32(RADEON_AIC_CNTL, tmp); in r100_pci_gart_enable()664 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN; in r100_pci_gart_enable()665 WREG32(RADEON_AIC_CNTL, tmp); in r100_pci_gart_enable()679 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS; in r100_pci_gart_disable()680 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); in r100_pci_gart_disable()814 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM; in r100_irq_process()815 WREG32(RADEON_AIC_CNTL, msi_rearm); in r100_irq_process()816 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM); in r100_irq_process()
308 (unsigned int)RADEON_READ(RADEON_AIC_CNTL)); in radeon_status()1106 tmp = RADEON_READ(RADEON_AIC_CNTL); in radeon_set_pcigart()1109 RADEON_WRITE(RADEON_AIC_CNTL, in radeon_set_pcigart()1127 RADEON_WRITE(RADEON_AIC_CNTL, in radeon_set_pcigart()
1059 #define RADEON_AIC_CNTL 0x01d0 macro
3365 #define RADEON_AIC_CNTL 0x01d0 macro