Searched refs:R2 (Results 1 - 200 of 204) sorted by relevance

12

/linux-4.4.14/arch/blackfin/lib/
H A Dmemset.S21 * R2 = count
28 P2 = R2 ; /* P2 = count */
29 R3 = R0 + R2; /* end */
30 CC = R2 <= 7(IU);
33 R2 = 3; define
34 R2 = R0 & R2; /* addr bottom two bits */ define
35 CC = R2 == 0; /* AZ set if zero. */
40 R2 = R1 << 8; /* create quad filler */ define
41 R2.L = R2.L + R1.L(NS);
42 R2.H = R2.L + R1.H(NS);
47 [P0++] = R2;
54 R2 = R3; /* end point */ define
56 R2 = R2 - R3; /* bytes left */ define
57 P2 = R2;
74 R0 = R0 - R2;
80 CC = R2 <= 2; /* 2 bytes */
H A Dmuldi3.S18 R1:R0 * R3:R2
19 = R1.h:R1.l:R0.h:R0.l * R3.h:R3.l:R2.h:R2.l
22 [X] + (R1.h * R2.h + R1.l * R3.l + R3.h * R0.h) * 2^64
23 [T1] + (R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h) * 2^48
24 [T2] + (R1.l * R2.l + R3.l * R0.l + R0.h * R2.h) * 2^32
25 [T3] + (R0.l * R2.h + R2.l * R0.h) * 2^16
26 [T4] + (R0.l * R2.l)
32 [E1] = R1.h * R2.l + R3.h * R0.l + R1.l * R2.h + R3.l * R0.h
33 [E2] = R1.l * R2.l + R3.l * R0.l + R0.h * R2.h
34 [E3] = R0.l * R2.h + R2.l * R0.h
35 [E4] = R0.l * R2.l
51 A0 = R2.H * R1.L, A1 = R2.L * R1.H (FU) || R3 = [SP + 12]; /* E1 */
56 A0 += R2.l * R1.l (FU); /* E2 */
58 A1 = R2.L * R0.L (FU); /* E4 */
61 A0 += R2.H * R0.H, A1 += R2.L * R0.H (FU); /* E2, E3c */
62 A1 += R0.L * R2.H (FU); /* E3c */
H A Dsmulsi3_highpart.S18 R2 = R1.L * R0.L (FU); define
22 R1.L = R2.H + R1.L;
24 R2 = cc; define
31 R1 = R1 + R2;
32 R2 = cc; define
33 R1 = R1 + R2;
H A Dudivsi3.S23 R2 = R1 << 16; define
24 CC = R2 <= R0 (IU);
27 R2 = R0 >> 31; /* if X is a 31-bit number */ define
29 R2 = R2 | R3; /* then it's okay to use the DIVQ builtins (fallthrough to fast)*/ define
30 CC = R2;
90 R2 = R0 >> 16; define
92 R2 = R3 - R2; /* shifted divisor < upper 16 bits of dividend */ define
103 /* Test for common identities. Value to be returned is placed in R2. */
111 R2.L = ONES R1;
112 R2 = R2.L (Z); define
113 CC = R2 == 1;
129 R2 = R1 >> 1; define
130 IF CC R1 = R2; /* Possibly-shifted R1 */
136 R2 = R0 >> 1; define
137 R2 = R0 >> 1; define
140 IF !CC R2 = R0; /* Shifted R0 */
150 .Lulst: R6 = R2 >> 31; /* R6 = sign bit of R2, for carry */
151 R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ define
162 .Lulend: R2 = R2 + R5; /* and "shift" it in. */
166 R6 = R2 << 1;
168 IF CC R2 = R6; /* if 1, Q = Q*2 */
171 R3 = R2; /* Copy of R2 */
176 R2 = R2 + R6; /* if yes, add one to quotient(Q) */ define
180 R0 = R2; /* Store quotient */
185 R2 = 0; define
187 R2 = -1 (X); /* X/0 => 0xFFFFFFFF */ define
190 R2 = -R2; /* R2 now 1 */ define
193 R2 = R0; /* X/1 => X */ define
197 R0 = R2;
213 R2 = R0 >> 31; define
233 R2 = R0; define
237 DIVQ(R2, R3); // 1
238 DIVQ(R2, R3); // 2
239 DIVQ(R2, R3); // 3
240 DIVQ(R2, R3); // 4
241 DIVQ(R2, R3); // 5
242 DIVQ(R2, R3); // 6
243 DIVQ(R2, R3); // 7
244 DIVQ(R2, R3); // 8
245 DIVQ(R2, R3); // 9
246 DIVQ(R2, R3); // 10
247 DIVQ(R2, R3); // 11
248 DIVQ(R2, R3); // 12
249 DIVQ(R2, R3); // 13
250 DIVQ(R2, R3); // 14
251 DIVQ(R2, R3); // 15
252 DIVQ(R2, R3); // 16
261 R3 = R2.L (Z); /* Q = X' / Y' */
262 R2 = R3; /* Preserve Q */ define
263 R2 *= R1; /* M = Q * Y */
264 R2 = R0 - R2; /* E = X - M */ define
270 R2 = R2 >> 16; /* E >> 16 */ define
271 CC = R2 == R3;
H A Ddivsi3.S22 * Registers Used : R2-R7,P0-P2
84 ** If the identity is true, return the value in R2.
100 R2.L = ONES R1;
101 R2 = R2.L (Z); define
102 CC = R2 == 1;
112 R2 = -R1; define
113 [--SP] = R2;
114 R2 = R0 << 1; /* R2 lsw of dividend */ define
119 R2 = R2 | R5; /* Shift quotient bit */ define
123 .Llst: R7 = R2 >> 31; /* record copy of carry from R2 */
124 R2 = R2 << 1; /* Shift 64 bit dividend up by 1 bit */ define
135 .Llend: R2 = R2 + R5; /* and then set shifted-in value to
149 R2 = -1 (X); define
150 R2 >>= 1;
154 R2 = 1 (Z); define
157 R2 = R0; /* assume divide by 1 => numerator */ define
161 R0 = R2; /* Return an identity value */
162 R2 = -R2; define
164 IF CC R0 = R2;
180 R2 = R0 >> 31; define
190 R2 = -R0; // negate result if necessary define
192 IF CC R0 = R2;
H A Douts.S16 CC = R2 == 0;
20 P2 = R2; /* P2 = count */
29 CC = R2 == 0;
33 P2 = R2; /* P2 = count */
42 CC = R2 == 0;
46 P2 = R2; /* P2 = count */
55 CC = R2 == 0;
59 P2 = R2; /* P2 = count */
H A Dstrncpy.S13 * R2 = size
27 CC = R2 == 0;
30 P2 = R2 ; /* size */
49 R2 = LC0; define
50 CC = R2
57 CC = R2 < R3;
60 R2 += -1;
65 * R2 = count (set above)
H A Dmemmove.S15 * R2 = count
23 P2 = R2; /* P2 = count */
29 R3 = R1 + R2;
34 CC = R2 <= R3;
45 R2 = R2 & R3; /* remainder */ define
46 P2 = R2; /* set remainder */
H A Dmemchr.S12 * R2 = count (n)
23 P2 = R2; /* P2 = count */
25 CC = R2 == 0;
H A Dstrncmp.S12 * R2 = size (n)
25 CC = R2 == 0;
37 R2 += -1; /* no, adjust count */
38 CC = R2 == 0;
H A Dumulsi3_highpart.S18 R2 = R1.H * R0.H, R3 = R1.L * R0.H (FU); define
28 R0 = R1 + R2;
H A Dmemcmp.S12 * R2 = count (n)
25 P2 = R2 ; /* P2 = count */
26 CC = R2 <= 7(IU);
36 R2 = R2 & R3; /* remainder */ define
37 P2 = R2; /* set remainder */
H A Dmemcpy.S18 * R2 = count
32 CC = R2 <= 0; /* length not positive? */
37 P2 = R2 ; /* length */
42 R3 = R1 + R2;
61 P2 = R2;
89 R3 = R2 & R3;
H A Dins.S79 P2 = R2; /* P2 = count */ \
/linux-4.4.14/arch/blackfin/mach-common/
H A Ddpmc_modes.S25 CLI R2;
28 STI R2;
34 R2 = IWR_DISABLE_ALL; define
73 R2 = IWR_DISABLE_ALL; define
83 CLI R2;
97 P5 = R2;
101 R2 = IWR_DISABLE_ALL; define
128 R2 = 0x0404(Z); define
129 R1 = R1|R2;
131 R2 = DEPOSIT(R7, R1); define
132 W[P0] = R2; /* Set Min Core Voltage */
156 R2 = IWR_DISABLE_ALL; define
196 R2 = [P0]; define
197 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
198 [P0] = R2;
201 R2 = [P0]; define
202 CC = BITTST(R2, 4);
210 R2 = [P0]; define
211 BITSET(R2, 24); /* SRFS enter self-refresh mode */
212 [P0] = R2;
216 R2 = w[P1]; define
218 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
221 R2 = [P0]; define
222 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
223 [P0] = R2;
234 R2 = [P0]; define
235 BITCLR(R2, 3); /* clear SRREQ bit */
236 [P0] = R2;
242 R2 = [P0]; define
243 BITSET(R2, 0); /* SCTLE enable CLKOUT */
244 [P0] = R2
248 R2 = [P0]; define
249 BITCLR(R2, 24); /* clear SRFS bit */
250 [P0] = R2
264 [P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
301 R2.H = .Lpm_resume_here;
302 R2.L = .Lpm_resume_here;
304 [P0++] = R2; /* Save Return Address */
H A Dcache.S31 R2 = -L1_CACHE_BYTES; define
34 R0 = R0 & R2;
38 R1 = R1 & R2;
42 R2 = R1 - R0; define
43 R2 >>= L1_CACHE_SHIFT;
44 P1 = R2;
H A Dinterrupt.S165 R2 = 10; define
176 CC = R1 == R2;
/linux-4.4.14/arch/x86/crypto/
H A Dtwofish-x86_64-asm_64.S52 #define R2 %rcx define
239 encrypt_round(R0,R1,R2,R3,0);
240 encrypt_round(R2,R3,R0,R1,8);
241 encrypt_round(R0,R1,R2,R3,2*8);
242 encrypt_round(R2,R3,R0,R1,3*8);
243 encrypt_round(R0,R1,R2,R3,4*8);
244 encrypt_round(R2,R3,R0,R1,5*8);
245 encrypt_round(R0,R1,R2,R3,6*8);
246 encrypt_round(R2,R3,R0,R1,7*8);
247 encrypt_round(R0,R1,R2,R3,8*8);
248 encrypt_round(R2,R3,R0,R1,9*8);
249 encrypt_round(R0,R1,R2,R3,10*8);
250 encrypt_round(R2,R3,R0,R1,11*8);
251 encrypt_round(R0,R1,R2,R3,12*8);
252 encrypt_round(R2,R3,R0,R1,13*8);
253 encrypt_round(R0,R1,R2,R3,14*8);
254 encrypt_last_round(R2,R3,R0,R1,15*8);
292 decrypt_round(R0,R1,R2,R3,15*8);
293 decrypt_round(R2,R3,R0,R1,14*8);
294 decrypt_round(R0,R1,R2,R3,13*8);
295 decrypt_round(R2,R3,R0,R1,12*8);
296 decrypt_round(R0,R1,R2,R3,11*8);
297 decrypt_round(R2,R3,R0,R1,10*8);
298 decrypt_round(R0,R1,R2,R3,9*8);
299 decrypt_round(R2,R3,R0,R1,8*8);
300 decrypt_round(R0,R1,R2,R3,7*8);
301 decrypt_round(R2,R3,R0,R1,6*8);
302 decrypt_round(R0,R1,R2,R3,5*8);
303 decrypt_round(R2,R3,R0,R1,4*8);
304 decrypt_round(R0,R1,R2,R3,3*8);
305 decrypt_round(R2,R3,R0,R1,2*8);
306 decrypt_round(R0,R1,R2,R3,1*8);
307 decrypt_last_round(R2,R3,R0,R1,0);
H A Dtwofish-i586-asm_32.S244 encrypt_round(R0,R1,R2,R3,0);
245 encrypt_round(R2,R3,R0,R1,8);
246 encrypt_round(R0,R1,R2,R3,2*8);
247 encrypt_round(R2,R3,R0,R1,3*8);
248 encrypt_round(R0,R1,R2,R3,4*8);
249 encrypt_round(R2,R3,R0,R1,5*8);
250 encrypt_round(R0,R1,R2,R3,6*8);
251 encrypt_round(R2,R3,R0,R1,7*8);
252 encrypt_round(R0,R1,R2,R3,8*8);
253 encrypt_round(R2,R3,R0,R1,9*8);
254 encrypt_round(R0,R1,R2,R3,10*8);
255 encrypt_round(R2,R3,R0,R1,11*8);
256 encrypt_round(R0,R1,R2,R3,12*8);
257 encrypt_round(R2,R3,R0,R1,13*8);
258 encrypt_round(R0,R1,R2,R3,14*8);
259 encrypt_last_round(R2,R3,R0,R1,15*8);
301 decrypt_round(R0,R1,R2,R3,15*8);
302 decrypt_round(R2,R3,R0,R1,14*8);
303 decrypt_round(R0,R1,R2,R3,13*8);
304 decrypt_round(R2,R3,R0,R1,12*8);
305 decrypt_round(R0,R1,R2,R3,11*8);
306 decrypt_round(R2,R3,R0,R1,10*8);
307 decrypt_round(R0,R1,R2,R3,9*8);
308 decrypt_round(R2,R3,R0,R1,8*8);
309 decrypt_round(R0,R1,R2,R3,7*8);
310 decrypt_round(R2,R3,R0,R1,6*8);
311 decrypt_round(R0,R1,R2,R3,5*8);
312 decrypt_round(R2,R3,R0,R1,4*8);
313 decrypt_round(R0,R1,R2,R3,3*8);
314 decrypt_round(R2,R3,R0,R1,2*8);
315 decrypt_round(R0,R1,R2,R3,1*8);
316 decrypt_last_round(R2,R3,R0,R1,0);
H A Daes-x86_64-asm_64.S26 #define R2 %rbx define
134 prologue(FUNC,KEY,B128,B192,R2,R8,R7,R9,R1,R3,R4,R6,R10,R5,R11)
136 #define return(FUNC) epilogue(FUNC,R8,R2,R9,R7,R5,R6,R3,R4,R11)
139 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4) \
140 move_regs(R1,R2,R5,R6)
143 round(TAB,OFFSET,R1,R2,R3,R4,R5,R6,R7,R10,R5,R6,R3,R4)
146 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4) \
147 move_regs(R1,R2,R5,R6)
150 round(TAB,OFFSET,R2,R1,R4,R3,R6,R5,R7,R10,R5,R6,R3,R4)
/linux-4.4.14/lib/
H A Dtest_bpf.c47 #define R2 BPF_REG_2 macro
405 insn[i++] = BPF_MOV64_IMM(R2, 1); bpf_fill_ld_abs_vlan_push_pop()
1058 BPF_ALU64_IMM(BPF_MOV, R2, 3),
1059 BPF_ALU64_REG(BPF_SUB, R1, R2),
1074 BPF_ALU64_IMM(BPF_MOV, R2, 3),
1075 BPF_ALU64_REG(BPF_MUL, R1, R2),
1090 BPF_ALU32_IMM(BPF_MOV, R2, 3),
1091 BPF_ALU64_REG(BPF_MUL, R1, R2),
1107 BPF_ALU32_IMM(BPF_MOV, R2, 3),
1108 BPF_ALU32_REG(BPF_MUL, R1, R2),
1128 BPF_ALU64_IMM(BPF_MOV, R2, 2),
1138 BPF_ALU64_IMM(BPF_ADD, R2, 20),
1148 BPF_ALU64_IMM(BPF_SUB, R2, 10),
1158 BPF_ALU64_REG(BPF_ADD, R0, R2),
1170 BPF_ALU64_REG(BPF_ADD, R1, R2),
1180 BPF_ALU64_REG(BPF_ADD, R2, R0),
1181 BPF_ALU64_REG(BPF_ADD, R2, R1),
1182 BPF_ALU64_REG(BPF_ADD, R2, R2),
1183 BPF_ALU64_REG(BPF_ADD, R2, R3),
1184 BPF_ALU64_REG(BPF_ADD, R2, R4),
1185 BPF_ALU64_REG(BPF_ADD, R2, R5),
1186 BPF_ALU64_REG(BPF_ADD, R2, R6),
1187 BPF_ALU64_REG(BPF_ADD, R2, R7),
1188 BPF_ALU64_REG(BPF_ADD, R2, R8),
1189 BPF_ALU64_REG(BPF_ADD, R2, R9), /* R2 == 1358 */
1190 BPF_JMP_IMM(BPF_JEQ, R2, 1358, 1),
1194 BPF_ALU64_REG(BPF_ADD, R3, R2),
1206 BPF_ALU64_REG(BPF_ADD, R4, R2),
1218 BPF_ALU64_REG(BPF_ADD, R5, R2),
1230 BPF_ALU64_REG(BPF_ADD, R6, R2),
1242 BPF_ALU64_REG(BPF_ADD, R7, R2),
1254 BPF_ALU64_REG(BPF_ADD, R8, R2),
1266 BPF_ALU64_REG(BPF_ADD, R9, R2),
1286 BPF_ALU32_IMM(BPF_MOV, R2, 2),
1295 BPF_ALU64_IMM(BPF_ADD, R2, 10),
1304 BPF_ALU32_REG(BPF_ADD, R0, R2),
1316 BPF_ALU32_REG(BPF_ADD, R1, R2),
1326 BPF_ALU32_REG(BPF_ADD, R2, R0),
1327 BPF_ALU32_REG(BPF_ADD, R2, R1),
1328 BPF_ALU32_REG(BPF_ADD, R2, R2),
1329 BPF_ALU32_REG(BPF_ADD, R2, R3),
1330 BPF_ALU32_REG(BPF_ADD, R2, R4),
1331 BPF_ALU32_REG(BPF_ADD, R2, R5),
1332 BPF_ALU32_REG(BPF_ADD, R2, R6),
1333 BPF_ALU32_REG(BPF_ADD, R2, R7),
1334 BPF_ALU32_REG(BPF_ADD, R2, R8),
1335 BPF_ALU32_REG(BPF_ADD, R2, R9), /* R2 == 1358 */
1336 BPF_JMP_IMM(BPF_JEQ, R2, 1358, 1),
1340 BPF_ALU32_REG(BPF_ADD, R3, R2),
1352 BPF_ALU32_REG(BPF_ADD, R4, R2),
1364 BPF_ALU32_REG(BPF_ADD, R5, R2),
1376 BPF_ALU32_REG(BPF_ADD, R6, R2),
1388 BPF_ALU32_REG(BPF_ADD, R7, R2),
1400 BPF_ALU32_REG(BPF_ADD, R8, R2),
1412 BPF_ALU32_REG(BPF_ADD, R9, R2),
1432 BPF_ALU64_IMM(BPF_MOV, R2, 2),
1442 BPF_ALU64_REG(BPF_SUB, R0, R2),
1454 BPF_ALU64_REG(BPF_SUB, R1, R2),
1463 BPF_ALU64_REG(BPF_SUB, R2, R0),
1464 BPF_ALU64_REG(BPF_SUB, R2, R1),
1465 BPF_ALU64_REG(BPF_SUB, R2, R3),
1466 BPF_ALU64_REG(BPF_SUB, R2, R4),
1467 BPF_ALU64_REG(BPF_SUB, R2, R5),
1468 BPF_ALU64_REG(BPF_SUB, R2, R6),
1469 BPF_ALU64_REG(BPF_SUB, R2, R7),
1470 BPF_ALU64_REG(BPF_SUB, R2, R8),
1471 BPF_ALU64_REG(BPF_SUB, R2, R9),
1472 BPF_ALU64_IMM(BPF_SUB, R2, 10),
1475 BPF_ALU64_REG(BPF_SUB, R3, R2),
1485 BPF_ALU64_REG(BPF_SUB, R4, R2),
1495 BPF_ALU64_REG(BPF_SUB, R5, R2),
1505 BPF_ALU64_REG(BPF_SUB, R6, R2),
1515 BPF_ALU64_REG(BPF_SUB, R7, R2),
1525 BPF_ALU64_REG(BPF_SUB, R8, R2),
1535 BPF_ALU64_REG(BPF_SUB, R9, R2),
1546 BPF_ALU64_REG(BPF_SUB, R0, R2),
1570 BPF_ALU64_REG(BPF_XOR, R2, R2),
1571 BPF_JMP_REG(BPF_JEQ, R1, R2, 1),
1573 BPF_ALU64_REG(BPF_SUB, R2, R2),
1577 BPF_JMP_REG(BPF_JEQ, R2, R3, 1),
1581 BPF_ALU64_IMM(BPF_MOV, R2, 1),
1631 BPF_ALU64_IMM(BPF_MOV, R2, 2),
1641 BPF_ALU64_REG(BPF_MUL, R0, R2),
1653 BPF_ALU64_REG(BPF_MUL, R1, R2),
1662 BPF_ALU64_REG(BPF_MOV, R2, R1),
1663 BPF_ALU64_IMM(BPF_RSH, R2, 32),
1664 BPF_JMP_IMM(BPF_JEQ, R2, 0x5a924, 1),
1670 BPF_ALU64_REG(BPF_MUL, R2, R0),
1671 BPF_ALU64_REG(BPF_MUL, R2, R1),
1672 BPF_ALU64_REG(BPF_MUL, R2, R3),
1673 BPF_ALU64_REG(BPF_MUL, R2, R4),
1674 BPF_ALU64_REG(BPF_MUL, R2, R5),
1675 BPF_ALU64_REG(BPF_MUL, R2, R6),
1676 BPF_ALU64_REG(BPF_MUL, R2, R7),
1677 BPF_ALU64_REG(BPF_MUL, R2, R8),
1678 BPF_ALU64_REG(BPF_MUL, R2, R9),
1679 BPF_ALU64_IMM(BPF_MUL, R2, 10),
1680 BPF_ALU64_IMM(BPF_RSH, R2, 32),
1681 BPF_ALU64_REG(BPF_MOV, R0, R2),
1693 BPF_ALU64_IMM(BPF_MOV, R2, 2),
1694 BPF_ALU64_IMM(BPF_XOR, R2, 3),
1695 BPF_ALU64_REG(BPF_DIV, R0, R2),
1716 BPF_MOV64_IMM(R2, 1),
1717 BPF_ALU64_REG(BPF_LSH, R0, R2),
1727 BPF_MOV64_IMM(R2, 1),
1728 BPF_ALU64_REG(BPF_LSH, R4, R2), /* R4 = 46 << 1 */
1751 BPF_ALU64_IMM(BPF_MOV, R2, 2),
1752 BPF_ALU32_REG(BPF_DIV, R0, R2),
2106 BPF_MOV64_REG(R2, R1),
2107 BPF_MOV64_REG(R3, R2),
2108 BPF_ALU64_IMM(BPF_RSH, R2, 32),
2112 BPF_JMP_IMM(BPF_JEQ, R2, 0x5678, 1),
2236 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
2238 BPF_ALU32_IMM(BPF_MOV, R2, 0xffffffff),
2239 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2272 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
2274 BPF_ALU64_IMM(BPF_MOV, R2, 0x0),
2275 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2288 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
2290 BPF_ALU64_IMM(BPF_MOV, R2, 0xffffffff),
2291 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2387 BPF_LD_IMM64(R2, 0x0),
2389 BPF_ALU32_IMM(BPF_ADD, R2, 0xffffffff),
2390 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2447 BPF_LD_IMM64(R2, 0x1),
2449 BPF_ALU64_IMM(BPF_ADD, R2, 0x0),
2450 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2463 BPF_LD_IMM64(R2, 0x0),
2465 BPF_ALU64_IMM(BPF_ADD, R2, 0xffffffff),
2466 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2701 BPF_LD_IMM64(R2, 0x1),
2703 BPF_ALU32_IMM(BPF_MUL, R2, 0xffffffff),
2704 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2761 BPF_LD_IMM64(R2, 0x1),
2763 BPF_ALU64_IMM(BPF_MUL, R2, 0xffffffff),
2764 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2826 BPF_LD_IMM64(R2, 0xffffffffffffffffLL),
2829 BPF_ALU64_REG(BPF_DIV, R2, R4),
2830 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2877 BPF_LD_IMM64(R2, 0xffffffffffffffffLL),
2879 BPF_ALU32_IMM(BPF_DIV, R2, 0xffffffff),
2880 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
2926 BPF_LD_IMM64(R2, 0xffffffffffffffffLL),
2928 BPF_ALU64_IMM(BPF_DIV, R2, 0xffffffff),
2929 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3152 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3154 BPF_ALU64_IMM(BPF_AND, R2, 0x0),
3155 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3168 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3170 BPF_ALU64_IMM(BPF_AND, R2, 0xffffffff),
3171 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3184 BPF_LD_IMM64(R2, 0xffffffffffffffffLL),
3186 BPF_ALU64_IMM(BPF_AND, R2, 0xffffffff),
3187 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3294 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3296 BPF_ALU64_IMM(BPF_OR, R2, 0x0),
3297 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3310 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3312 BPF_ALU64_IMM(BPF_OR, R2, 0xffffffff),
3313 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3326 BPF_LD_IMM64(R2, 0x0000000000000000LL),
3328 BPF_ALU64_IMM(BPF_OR, R2, 0xffffffff),
3329 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3436 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3438 BPF_ALU64_IMM(BPF_XOR, R2, 0x0),
3439 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3452 BPF_LD_IMM64(R2, 0x0000ffffffff0000LL),
3454 BPF_ALU64_IMM(BPF_XOR, R2, 0xffffffff),
3455 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3468 BPF_LD_IMM64(R2, 0x0000000000000000LL),
3470 BPF_ALU64_IMM(BPF_XOR, R2, 0xffffffff),
3471 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
3940 BPF_LD_IMM64(R2, 0xffff00000000ffffLL),
3943 BPF_LDX_MEM(BPF_DW, R2, R10, -40),
3944 BPF_JMP_REG(BPF_JEQ, R2, R3, 2),
4215 BPF_LD_IMM64(R2, -2),
4216 BPF_JMP_REG(BPF_JSGT, R1, R2, 1),
4230 BPF_LD_IMM64(R2, -1),
4231 BPF_JMP_REG(BPF_JSGT, R1, R2, 1),
4246 BPF_LD_IMM64(R2, -2),
4247 BPF_JMP_REG(BPF_JSGE, R1, R2, 1),
4261 BPF_LD_IMM64(R2, -1),
4262 BPF_JMP_REG(BPF_JSGE, R1, R2, 1),
4277 BPF_LD_IMM64(R2, 2),
4278 BPF_JMP_REG(BPF_JGT, R1, R2, 1),
4293 BPF_LD_IMM64(R2, 2),
4294 BPF_JMP_REG(BPF_JGE, R1, R2, 1),
4308 BPF_LD_IMM64(R2, 3),
4309 BPF_JMP_REG(BPF_JGE, R1, R2, 1),
4324 BPF_LD_IMM64(R2, 2),
4325 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
4340 BPF_LD_IMM64(R2, 3),
4341 BPF_JMP_REG(BPF_JEQ, R1, R2, 1),
4356 BPF_LD_IMM64(R2, 2),
4357 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
4371 BPF_LD_IMM64(R2, 0xffffffff),
4372 BPF_JMP_REG(BPF_JNE, R1, R2, 1),
/linux-4.4.14/arch/mips/include/uapi/asm/
H A Dswab.h50 * Having already checked for MIPS R2, enable the optimized version for
69 #endif /* (not __mips16) and (MIPS R2 or newer or Loongson 3A) */
/linux-4.4.14/arch/blackfin/mach-bf609/
H A Ddpm.S136 R2.H = .Lpm_resume_here;
137 R2.L = .Lpm_resume_here;
139 [P0++] = R2;
/linux-4.4.14/arch/hexagon/kernel/
H A Dvm_entry.S74 R2.H = #HI(_THREAD_SIZE); } \
77 R2.L = #LO(_THREAD_SIZE); } \
80 R2 = neg(R2); } \ define
83 R2 = and(R0,R2); } \ define
85 THREADINFO_REG = R2; } \
88 R2 = #-1; } \ define
89 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
125 R2 = #-1; } \ define
126 { memw(R0 + #_PT_SYSCALL_NR) = R2; \
213 * Need to save off R0, R1, R2, R3 immediately.
H A Dvm_switch.S47 * in the new R0's pointer. Technically it should be R2, but they should
H A Dhead.S132 * Note that in this version, R1 and R2 get "clobbered"; see
204 /* Fixme: THREADINFO_REG can't be R2 because of that memset thing. */
/linux-4.4.14/arch/powerpc/kvm/
H A Dbook3s_32_sr.S32 * R2 = host R2
88 * R2 = host R2
H A Dbook3s_64_slb.S37 * R2 = host R2
103 * R2 = host R2
H A Dbook3s_segment.S61 * R2 = host R2
81 /* Save R1/R2 in the PACA (64-bit) or shadow_vcpu (32-bit) */
201 /* Restore R1/R2 so we can handle faults */
359 * R2 = host R2
H A Dbook3s_hv_interrupts.S145 * R2 = host R2
H A Dbook3s_interrupts.S151 * R2 = host R2
H A Dbooke_interrupts.S220 stw r2, VCPU_GPR(R2)(r4)
428 lwz r2, VCPU_GPR(R2)(r4)
H A Dbookehv_interrupts.S74 PPC_STL r2, VCPU_GPR(R2)(r4)
651 PPC_LL r2, VCPU_GPR(R2)(r4)
H A Dbook3s_hv_rmhandlers.S487 * R2 = TOC
1044 ld r2, VCPU_GPR(R2)(r4)
1128 std r2, VCPU_GPR(R2)(r9)
1152 /* Restore R1/R2 so we can handle faults */
/linux-4.4.14/sound/pci/oxygen/
H A Dwm8785.h37 /* R2 */
/linux-4.4.14/tools/perf/arch/arm/util/
H A Dunwind-libdw.c19 dwarf_regs[2] = REG(R2); libdw__arch_set_initial_registers()
/linux-4.4.14/arch/mips/include/asm/
H A Dirq.h41 * Before R2 the timer and performance counter interrupts were both fixed to
42 * IE7. Since R2 their number has to be read from the c0_intctl register.
H A Dcpu-type.h75 * All MIPS64 R2 processors have their own special symbols. That is, __get_cpu_type()
76 * there currently is no pure R2 core __get_cpu_type()
H A Dmips-r2-to-r6-emul.h93 /* MIPS R2 Emulator ON/OFF */
H A Dcpu-features.h251 * an IHB instruction to deal with an instruction hazard as per MIPS R2
293 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH.
294 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD.
H A Dpgtable-bits.h115 /* R2 or later cores check for RI/XI support to determine _PAGE_READ */
191 * 64-bit, R2 or later: CCC D V G RI/R XI [S H] M A W P
192 * 32-bit, R2 or later: CCC D V G RI/R XI M A W P
H A Dhazards.h81 * run fine on R2 processors.
411 * MIPS R2 instruction hazard barrier. Needs to be called as a subroutine.
H A Dthread_info.h30 int r2_emul_return; /* 1 => Returning from R2 emulator */
H A Delf.h27 #define EF_MIPS_ARCH_32R2 0x70000000 /* MIPS32 R2 code. */
28 #define EF_MIPS_ARCH_64R2 0x80000000 /* MIPS64 R2 code. */
/linux-4.4.14/tools/perf/arch/arm/tests/
H A Dregs_load.S5 #define R2 0x10 define
42 str r2, [r0, #R2]
/linux-4.4.14/arch/parisc/kernel/
H A Dunaligned.c120 #define R2(i) (((i)>>16)&0x1f) macro
508 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0)<<shift; handle_unaligned()
510 newbase += (R2(regs->iir)?regs->gr[R2(regs->iir)]:0); handle_unaligned()
557 ret = emulate_sth(regs, R2(regs->iir)); handle_unaligned()
562 ret = emulate_stw(regs, R2(regs->iir),0); handle_unaligned()
575 ret = emulate_std(regs, R2(regs->iir),0); handle_unaligned()
619 ret = emulate_ldd(regs,R2(regs->iir),1); handle_unaligned()
623 ret = emulate_std(regs, R2(regs->iir),1); handle_unaligned()
626 ret = emulate_ldd(regs, R2(regs->iir),0); handle_unaligned()
629 ret = emulate_std(regs, R2(regs->iir),0); handle_unaligned()
637 ret = emulate_ldw(regs, R2(regs->iir),0); handle_unaligned()
640 ret = emulate_ldw(regs, R2(regs->iir),1); handle_unaligned()
645 ret = emulate_stw(regs, R2(regs->iir),1); handle_unaligned()
648 ret = emulate_stw(regs, R2(regs->iir),0); handle_unaligned()
654 ret = emulate_ldh(regs, R2(regs->iir)); handle_unaligned()
658 ret = emulate_ldw(regs, R2(regs->iir),0); handle_unaligned()
661 ret = emulate_sth(regs, R2(regs->iir)); handle_unaligned()
665 ret = emulate_stw(regs, R2(regs->iir),0); handle_unaligned()
/linux-4.4.14/sound/soc/codecs/
H A Drt5640.c546 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
562 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_STO_DAC_MIXER,
571 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
578 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_DAC_MIXER,
594 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_DIG_MIXER,
650 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_SPK_R_MIXER,
665 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_L3_MIXER,
686 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_OUT_R3_MIXER,
766 SOC_DAPM_SINGLE("DAC R2 Switch", RT5640_MONO_MIXER,
847 "DMIC R1", "DMIC R2", "Mono DAC MIXR"
1080 SND_SOC_DAPM_PGA("DMIC R2", SND_SOC_NOPM, 0, 0, NULL, 0),
1113 SND_SOC_DAPM_MUX("Stereo ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1125 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1268 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5640_dac_r2_mux),
1275 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5640_PWR_DIG1, RT5640_PWR_DAC_R2_BIT,
1307 SND_SOC_DAPM_SUPPLY("DAC R2 Filter", RT5640_PWR_DIG1,
1329 {"DMIC R2", NULL, "DMIC2"},
1364 {"DMIC R2", NULL, "DMIC CLK"},
1365 {"DMIC R2", NULL, "DMIC2 Power"},
1375 {"Stereo ADC R2 Mux", "DMIC1", "DMIC R1"},
1376 {"Stereo ADC R2 Mux", "DMIC2", "DMIC R2"},
1377 {"Stereo ADC R2 Mux", "DIG MIX", "DIG MIXR"},
1387 {"Mono ADC R2 Mux", "DMIC R1", "DMIC R1"},
1388 {"Mono ADC R2 Mux", "DMIC R2", "DMIC R2"},
1389 {"Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR"},
1397 {"Stereo ADC MIXR", "ADC2 Switch", "Stereo ADC R2 Mux"},
1407 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
1567 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1571 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1575 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
1577 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1580 {"DIG MIXR", "DAC R2 Switch", "DAC R2 Mux"},
1585 {"DAC R2", NULL, "Mono DAC MIXR"},
1586 {"DAC R2", NULL, "PLL1", is_sys_clk_from_pll},
1589 {"SPK MIXR", "DAC R2 Switch", "DAC R2"},
1594 {"OUT MIXL", "DAC R2 Switch", "DAC R2"},
1598 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
1601 {"HPO MIX R", "HPO MIX DAC2 Switch", "DAC R2"},
1603 {"Mono MIX", "DAC R2 Switch", "DAC R2"},
1616 {"Stereo DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1619 {"Mono DAC MIXL", "DAC R2 Switch", "IF2 DAC R"},
1621 {"Mono DAC MIXR", "DAC R2 Switch", "IF2 DAC R"},
1625 {"DIG MIXR", "DAC R2 Switch", "IF2 DAC R"},
1628 {"IF2 DAC R", NULL, "DAC R2 Filter"},
H A Drt5645.c896 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_STO_DAC_MIXER,
907 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
914 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_MONO_DAC_MIXER,
925 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
932 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_DIG_MIXER,
979 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_SPK_R_MIXER,
1003 SOC_DAPM_SINGLE("DAC R2 Switch", RT5645_OUT_R1_MIXER,
1809 SND_SOC_DAPM_INPUT("DMIC R2"),
1856 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1872 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1947 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5645_dac_r2_mux),
1950 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5645_PWR_DIG1,
1983 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5645_PWR_DIG1, RT5645_PWR_DAC_R2_BIT,
2116 { "DMIC2", NULL, "DMIC R2" },
2151 {"DMIC R2", NULL, "DMIC CLK"},
2152 {"DMIC R2", NULL, "DMIC2 Power"},
2163 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2173 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2174 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2183 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2184 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2189 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2205 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2260 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2261 { "DAC R2 Mux", "Mono ADC", "Mono ADC MIXR" },
2262 { "DAC R2 Mux", "Haptic", "Haptic Generator" },
2263 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2264 { "DAC R2 Volume", NULL, "dac mono right filter" },
2272 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2277 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2280 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2286 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2288 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2294 { "DAC R2", NULL, "PLL1", is_sys_clk_from_pll },
2303 { "SPK MIXR", "DAC R2 Switch", "DAC R2" },
2312 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2321 { "HPOVOL MIXR", "DAC2 Switch", "DAC R2" },
2327 { "DAC 2", NULL, "DAC R2" },
2396 { "DAC R2", NULL, "A DAC2 R Mux" },
2470 { "DAC R2 Mux", "IF1 DAC", "RT5650 IF1 DAC2 R Mux" },
2477 { "DAC R2", NULL, "Mono DAC MIXR" },
2528 { "DAC R2 Mux", "IF1 DAC", "RT5645 IF1 DAC2 R Mux" },
H A Drt5670.c926 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_STO_DAC_MIXER,
937 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
944 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DD_MIXER,
955 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
962 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_DIG_MIXER,
1003 SOC_DAPM_SINGLE("DAC R2 Switch", RT5670_OUT_R1_MIXER,
1180 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5670_stereo1_adc2_enum);
1189 SOC_DAPM_ENUM("Stereo2 ADC R2 source", rt5670_stereo2_adc2_enum);
1589 SND_SOC_DAPM_INPUT("DMIC R2"),
1645 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1655 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1673 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1796 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0,
1800 SND_SOC_DAPM_PGA("DAC R2 Volume", RT5670_PWR_DIG1,
1842 SND_SOC_DAPM_DAC("DAC R2", NULL, RT5670_PWR_DIG1,
1938 { "DMIC2", NULL, "DMIC R2" },
1972 { "DMIC R2", NULL, "DMIC CLK" },
1973 { "DMIC R2", NULL, "DMIC2 Power" },
1992 { "Mono DMIC R Mux", "DMIC2", "DMIC R2" },
2005 { "Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC Mux" },
2006 { "Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2015 { "Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux" },
2016 { "Mono ADC R2 Mux", "Mono DAC MIXR", "Mono DAC MIXR" },
2021 { "Sto1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux" },
2037 { "Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux" },
2048 { "Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC Mux" },
2049 { "Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR" },
2054 { "Sto2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux" },
2199 { "DAC R2 Mux", "IF1 DAC", "IF1 DAC2 R" },
2200 { "DAC R2 Mux", "IF2 DAC", "IF2 DAC R" },
2201 { "DAC R2 Mux", "TxDC DAC", "TxDC_DAC" },
2202 { "DAC R2 Mux", "TxDP ADC", "TxDP_ADC" },
2203 { "DAC R2 Volume", NULL, "DAC R2 Mux" },
2204 { "DAC R2 Volume", NULL, "DAC Mono Right Filter" },
2213 { "Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2219 { "Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2222 { "Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2228 { "DAC MIXL", "DAC R2 Switch", "DAC R2 Volume" },
2230 { "DAC MIXR", "DAC R2 Switch", "DAC R2 Volume" },
2238 { "DAC R2", NULL, "Mono DAC MIXR" },
2247 { "OUT MIXR", "DAC R2 Switch", "DAC R2" },
2256 { "DAC 2", NULL, "DAC R2" },
H A Drt5651.c463 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_STO_DAC_MIXER,
474 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
481 SOC_DAPM_SINGLE("DAC R2 Switch", RT5651_DD_MIXER,
649 SOC_DAPM_ENUM("Stereo1 ADC R2 source", rt5651_stereo1_adc2_enum);
977 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
989 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
1051 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5651_dac_r2_mux),
1053 SND_SOC_DAPM_PGA("DAC R2 Volume", SND_SOC_NOPM, 0, 0, NULL, 0),
1186 {"Stereo1 ADC R2 Mux", "DMIC", "DMIC R1"},
1187 {"Stereo1 ADC R2 Mux", "DD MIX", "DD MIXR"},
1196 {"Stereo2 ADC R2 Mux", "DMIC R", "DMIC R1"},
1197 {"Stereo2 ADC R2 Mux", "DD MIXR", "DD MIXR"},
1206 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
1216 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
1258 {"DAC R2 Mux", "IF1", "IF1 DAC2 R"},
1259 {"DAC R2 Mux", "IF2", "IF2 DAC R"},
1260 {"DAC R2 Volume", NULL, "DAC R2 Mux"},
1268 {"Stereo DAC MIXR", "DAC R2 Switch", "DAC R2 Volume"},
1287 {"DD MIXL", "DAC R2 Switch", "DAC R2 Volume"},
1291 {"DD MIXR", "DAC R2 Switch", "DAC R2 Volume"},
H A Dwm8523.h53 * R2 (0x02) - PSCTRL1
H A Dwm8983.c33 { 0x02, 0x0000 }, /* R2 - Power management 2 */
325 SOC_DAPM_SINGLE("R2 Switch", WM8983_INPUT_CTRL, 6, 1, 0),
356 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8983_RIGHT_ADC_BOOST_CTRL,
424 SND_SOC_DAPM_INPUT("R2"),
472 { "Right Boost Mixer", "R2 Volume", "R2" },
483 { "Right Input Mixer", "R2 Switch", "R2" },
H A Dwm8985.c45 { 2, 0x0000 }, /* R2 - Power management 2 */
405 SOC_DAPM_SINGLE("R2 Switch", WM8985_INPUT_CTRL, 6, 1, 0),
418 SOC_DAPM_SINGLE_TLV("R2 Volume", WM8985_RIGHT_ADC_BOOST_CTRL,
474 SND_SOC_DAPM_INPUT("R2"),
506 { "Right Boost Mixer", "R2 Volume", "R2" },
517 { "Right Input Mixer", "R2 Switch", "R2" },
H A Dtwl4030.c1230 SND_SOC_DAPM_MIXER("Digital R2 Playback Mixer",
1242 SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer",
1402 {"Digital R2 Playback Mixer", NULL, "DAC Right2"},
1414 {"Digital R2 Playback Mixer", NULL, "AIF Enable"},
1420 {"Analog R2 Playback Mixer", NULL, "Digital R2 Playback Mixer"},
1434 {"PredriveL Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1439 {"PredriveR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1450 {"HeadsetR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1460 {"CarkitR Mixer", "AudioR2", "Analog R2 Playback Mixer"},
1466 {"HandsfreeL Mux", "AudioR2", "Analog R2 Playback Mixer"},
1472 {"HandsfreeR Mux", "AudioR2", "Analog R2 Playback Mixer"},
1566 {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
1575 {"Digital R2 Playback Mixer", NULL, "Right Digital Loopback"},
H A Dwm8741.h63 * R2 (0x02) - DACRLSB_ATTENUATION
H A Dwm8978.c239 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
288 SOC_DAPM_SINGLE("R2 Switch", WM8978_INPUT_CONTROL, 6, 1, 0),
346 SND_SOC_DAPM_INPUT("R2"),
381 {"Right Boost Mixer", NULL, "R2"},
393 {"Right Input Mixer", "R2 Switch", "R2"},
H A Dsta529.c100 { 2, 0x50 }, /* R2 - Master Volume */
H A Dwm8737.h66 * R2 (0x02) - AUDIO path L
H A Dwm8955.h59 * R2 (0x02) - LOUT1 volume
H A Dwm8523.c51 { 2, 0x0000 }, /* R2 - PSCTRL1 */
H A Dwm9090.c39 { 2, 0x6000 }, /* R2 - Power Management (2) */
H A Dwm8737.c52 { 2, 0x0007 }, /* R2 - AUDIO path L */
H A Dwm8741.c54 { 2, 0x0000 }, /* R2 - DACRLSB Attenuation */
H A Dwm8955.c53 { 2, 0x0079 }, /* R2 - LOUT1 volume */
H A Dwm8961.c38 { 2, 0x0000 }, /* R2 - LOUT1 volume */
H A Dwm8961.h141 * R2 (0x02) - LOUT1 volume
H A Dwm8990.h114 * R2 (0x02) - Power Management (2)
H A Dwm8991.h112 * R2 (0x02) - Power Management (2)
H A Dwm9081.h98 * R2 (0x02) - Analogue Lineout
H A Dwm9090.h112 * R2 (0x02) - Power Management (2)
H A Drt5677.c2671 SND_SOC_DAPM_INPUT("DMIC R2"),
3210 { "DMIC2", NULL, "DMIC R2" },
3219 { "DMIC R2", NULL, "DMIC CLK" },
4106 { "DMIC R2", NULL, "DMIC1 power" },
4111 { "DMIC R2", NULL, "DMIC2 power" },
H A Dwm8983.h124 * R2 (0x02) - Power management 2
H A Dwm8985.h119 * R2 (0x02) - Power management 2
H A Dwm8990.c51 { 2, 0x6000 }, /* R2 - Power Management (2) */
H A Dwm8991.c41 { 2, 0x6000 }, /* R2 - Power Management (2) */
H A Dwm8993.c46 { 2, 0x6000 }, /* R2 - Power Management (2) */
H A Dwm9081.c34 { 2, 0x00B9 }, /* R2 - Analogue Lineout */
H A Dalc5632.c39 { 2, 0x8080 }, /* R2 - Speaker Output Volume */
H A Dwm8993.h180 * R2 (0x02) - Power Management (2)
H A Dwm8962.c119 { 2, 0x0000 }, /* R2 - HPOUTL volume */
/linux-4.4.14/drivers/media/usb/dvb-usb/
H A Ddigitv.h23 * <cmdbyte> VV <len> R0 R1 R2 R3
/linux-4.4.14/arch/arm/mach-iop13xx/
H A Dirq.c56 /* INTCTL2 CP6 R2 Page 4
96 /* INTSTR2 CP6 R2 Page 5
117 /* INTSIZE CP6 R2 Page 2
/linux-4.4.14/arch/powerpc/include/asm/
H A Dkgdb.h59 /* CR/LR, R1, R2, R13-R31 inclusive. */
H A Dreg_booke.h309 #define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */
/linux-4.4.14/arch/mips/kernel/
H A Dcsrc-r4k.c77 * R2 onwards makes the count accessible to user mode so it can be used init_r4k_clocksource()
H A Dmips-r2-to-r6-emul.c10 * MIPS R2 user space instruction emulator for MIPS R6
64 pr_info("MIPS R2-to-R6 Emulator Enabled!"); mipsr2emu_enable()
71 * mipsr6_emul - Emulate some frequent R2/R5/R6 instructions in delay slot
257 /* Roll back to the reserved R2 JR instruction */ jr_func()
900 * mipsr2_decoder: Decode and emulate a MIPS R2 instruction
923 pr_debug("Emulating the 0x%08x R2 instruction @ 0x%08lx (pass=%d))\n", mipsr2_decoder()
1980 * an exception. MIPS R2 LL/SC instructions trap with an mipsr2_decoder()
2036 * an exception. MIPS R2 LL/SC instructions trap with an mipsr2_decoder()
2099 * an exception. MIPS R2 LL/SC instructions trap with an mipsr2_decoder()
2160 * an exception. MIPS R2 LL/SC instructions trap with an mipsr2_decoder()
2206 * it's likely we have more R2 instructions to emulate mipsr2_decoder()
H A Dcevt-r4k.c60 * Before R2 of the architecture there was no way to see if a c0_compare_interrupt()
H A Dtraps.c1079 * Avoid any kernel code. Just emulate the R2 instruction do_ri()
2120 * Before R2 both interrupt numbers were fixed to 7, so on R2 only: per_cpu_trap_init()
H A Dbranch.c848 pr_info("%s: R2 branch but r2-to-r6 emulator is not preset - sending SIGILL.\n", __compute_return_epc_for_insn()
H A Dcpu-probe.c1525 /* R2 has Performance Counter Interrupt indicator */ cpu_probe()
/linux-4.4.14/arch/arm/include/asm/
H A Ddiv64.h182 "umlal %R0, %Q0, %Q1, %R2\n\t" \
184 "umlal %Q0, %R0, %R1, %R2" \
189 asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \
194 "umlal %Q0, %R0, %R2, %R3" \
H A Duaccess.h463 #define __reg_oper0 "%R2"
467 #define __reg_oper1 "%R2"
/linux-4.4.14/arch/sparc/net/
H A Dbpf_jit_comp.c298 #define emit_cmp(R1, R2) \
299 *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
304 #define emit_btst(R1, R2) \
305 *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
310 #define emit_sub(R1, R2, R3) \
311 *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
316 #define emit_add(R1, R2, R3) \
317 *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
322 #define emit_and(R1, R2, R3) \
323 *prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))
/linux-4.4.14/include/linux/mmc/
H A Dmmc.h31 #define MMC_ALL_SEND_CID 2 /* bcr R2 */
38 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */
39 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */
156 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS
157 * R1 is the low order byte; R2 is the next highest byte, when present.
/linux-4.4.14/arch/blackfin/mach-bf561/
H A Dsecondary.S140 CLI R2;
143 STI R2;
/linux-4.4.14/arch/blackfin/kernel/
H A Dfixed_code.S50 * R2: new value to store
59 [P0] = R2;
H A Dftrace-entry.S27 * save/restore the registers used for argument passing (R0-R2) in case
H A Dpseudodbg.c13 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
H A Dtrace.c959 pr_notice(" R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
/linux-4.4.14/drivers/mmc/host/
H A Dandroid-goldfish.c75 /* MMC response (or R2 bits 0 - 31) */
78 /* MMC R2 response bits 32 - 63 */
81 /* MMC R2 response bits 64 - 95 */
84 /* MMC R2 response bits 96 - 127 */
H A Dushc.c13 * - Version 2 devices only support SDIO cards/devices (R2 response is
265 /* Version 2 firmware doesn't support the R2 response format. */ ushc_request()
H A Dmmc_spi.c255 case MMC_RSP_SPI_R2: return "R2/R5"; maptype()
367 /* SPI R2 == R1 + second status byte; SEND_STATUS mmc_spi_response_get()
479 * + second status byte, for R2 responses mmc_spi_command_send()
514 if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ mmc_spi_command_send()
H A Dtoshsd.c222 /* R2 */ toshsd_cmd_irq()
H A Drtsx_usb_sdmmc.c317 * R2 sd_send_cmd_get_rsp()
440 * of response type R2. Assign dummy CRC, 0, and end bit to the sd_send_cmd_get_rsp()
H A Ddavinci_mmc.c299 s = ", R2 response"; mmc_davinci_start_command()
H A Drtsx_pci_sdmmc.c317 * of response type R2. Assign dummy CRC, 0, and end bit to the sd_send_cmd_get_rsp()
H A Ds3cmci.c184 " R2:[%08x] R3:[%08x]\n", dbg_dumpregs()
H A Dsh_mmcif.c76 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
H A Dusdhi6rol0.c1177 * R2-type response: usdhi6_resp_read()
/linux-4.4.14/drivers/pci/hotplug/
H A Dcpci_hotplug.h35 /* PICMG 2.1 R2.0 HS CSR bits: */
H A Dcpci_hotplug_core.c359 * According to PICMG 2.1 R2.0, section 6.3.2, upon
/linux-4.4.14/arch/arm/probes/kprobes/
H A Dactions-common.c141 /* Instruction only uses registers in the range R2..R14 */ kprobe_decode_ldmstm()
/linux-4.4.14/arch/arm/mach-iop13xx/include/mach/
H A Dirqs.h25 /* INTPND2 CP6 R2 Page 3
/linux-4.4.14/arch/s390/include/asm/
H A Dkvm_para.h14 * s390 ABI, so we use R2-R6 for parameters 1-5. In addition we use R1
16 * written to R2. We use the diagnose instruction as hypercall. To avoid
/linux-4.4.14/arch/parisc/include/asm/
H A Duaccess.h185 "\n2:\tstw %R2,4(%1)\n\t" \
196 "\n2:\tstw %R2,4(%%sr3,%1)\n\t" \
/linux-4.4.14/arch/arm/vfp/
H A Dvfp.h50 "adcs %R0, %R2, %R4\n\t" add128()
63 "sbcs %R0, %R2, %R4\n\t" sub128()
/linux-4.4.14/kernel/bpf/
H A Dhelpers.c32 * and R2 points to a program stack and map->key_size bytes were bpf_map_lookup_elem()
H A Dverifier.c103 * BPF_MOV64_REG(BPF_REG_2, BPF_REG_10), // after this insn R2 type is FRAME_PTR
104 * BPF_ALU64_IMM(BPF_ADD, BPF_REG_2, -4), // after this insn R2 type is PTR_TO_STACK
111 * Then .arg2_type == ARG_PTR_TO_MAP_KEY and R2->type == PTR_TO_STACK, ok so far,
112 * Now verifier checks that [R2, R2 + map's key_size) are within stack limits
1079 /* case: R1 = R2 check_alu_op()
/linux-4.4.14/arch/sh/kernel/
H A Dprocess_32.c48 printk("R0 : %08lx R1 : %08lx R2 : %08lx R3 : %08lx\n", show_regs()
H A Dentry-common.S195 ! ptrace(POKEUSR). (Note that R0-R2 are
270 * Arguments #4 to #6: R0, R1, R2
H A Dprocess_64.c73 printk("R0 : %08Lx%08Lx R1 : %08Lx%08Lx R2 : %08Lx%08Lx\n", show_regs()
/linux-4.4.14/arch/m32r/kernel/
H A Dprocess.c82 printk("R0 [%08lx]:R1 [%08lx]:R2 [%08lx]:R3 [%08lx]\n", \ show_regs()
H A Dentry.S90 #define R2(reg) @(0x18,reg) define
254 ld r2, R2(sp)
/linux-4.4.14/arch/arm/mach-omap2/
H A Dsleep24xx.S47 * R2 : SDRC_POWER
/linux-4.4.14/arch/arm/mach-pxa/
H A Dcsb726.c38 * XXX: 79 CS_3 for LAN9215 or PSKTSEL on R2, R3
/linux-4.4.14/sound/soc/rockchip/
H A Drockchip_rt5645.c52 {"DMIC R2", NULL, "Int Mic"},
/linux-4.4.14/include/linux/iio/frequency/
H A Dad9523.h131 * @pll2_r2_div: PLL2 R2 divider, range 0..31.
/linux-4.4.14/drivers/media/dvb-frontends/
H A Ddrxd_hard.c94 u16 R2; member in struct:SCfgAgc
880 R2 ReadIFAgc()
885 u32 R2 = state->if_agc_cfg.R2; ReadIFAgc() local
890 if (R2 == 0 && (R1 == 0 || R3 == 0)) ReadIFAgc()
893 Vmax = (3300 * R2) / (R1 + R2); ReadIFAgc()
894 Rpar = (R2 * R3) / (R3 + R2); ReadIFAgc()
2515 state->if_agc_cfg.R2 = (u16) (ulIfAgcR2); CDRXD()
2519 state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2); CDRXD()
H A Ddvb-pll.c513 /* byte 4 : 1 * * AGD R3 R2 R1 R0
515 * AGD = 1, R3 R2 R1 R0 = 0 1 0 1 => byte 4 = 1**10101 = 0x95
H A Dzl10036.c173 * 5[0x00]: P0 | C1 | C0 | R4 | R3 | R2 | R1 | R0
/linux-4.4.14/samples/bpf/
H A Dtest_verifier.c201 .errstr = "R2 !read_ok",
299 /* fill it back into R2 */
302 /* should be able to access R0 = *(R2 + 8) */
1166 .errstr_unpriv = "R2 pointer comparison",
1179 .errstr_unpriv = "R2 pointer arithmetic",
/linux-4.4.14/drivers/platform/x86/
H A Dalienware-wmi.c100 .ident = "Alienware X51 R2",
103 DMI_MATCH(DMI_PRODUCT_NAME, "Alienware X51 R2"),
/linux-4.4.14/drivers/acpi/acpica/
H A Dutosi.c100 {"Windows 2009", NULL, 0, ACPI_OSI_WIN_7}, /* Windows 7 and Server 2008 R2 - Added 09/2009 */
102 {"Windows 2013", NULL, 0, ACPI_OSI_WIN_8}, /* Windows 8.1 and Server 2012 R2 - Added 01/2014 */
/linux-4.4.14/arch/arc/kernel/
H A Dsetup.c157 { {0x50, "ARC HS38 R2.0"}, 0x51},
158 { {0x52, "ARC HS38 R2.1"}, 0x52},
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A Dkgdb_asm.S33 move.d $r2, [$acr] ; Save R2
475 move.d [$acr], $r2 ; Restore R2
H A Dkgdb.c311 R0, R1, R2, R3, enumerator in enum:register_name
/linux-4.4.14/arch/mips/include/asm/netlogic/
H A Dmips-extns.h43 * On non-R2 platforms the flags has part of EIMR that is shadowed in STATUS
/linux-4.4.14/arch/sh/kernel/cpu/sh2/
H A Dentry.S107 mov.l @r2+,r0 ! old R2
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
H A Dentry.S90 mov.l @r8+,r2 ! old R2
/linux-4.4.14/arch/m68k/include/asm/
H A Duaccess_mm.h103 "2: "MOVES".l %R2,(%1)\n" \
/linux-4.4.14/arch/arm/mach-pxa/include/mach/
H A Dpxa3xx-regs.h107 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
/linux-4.4.14/sound/pci/ali5451/
H A Dali5451.c648 u8 bval, R1 = 0, R2; snd_ali_detect_spdif_rate() local
669 R2 = bval & 0x1F; snd_ali_detect_spdif_rate()
670 if (R2 != R1) snd_ali_detect_spdif_rate()
671 R1 = R2; snd_ali_detect_spdif_rate()
681 if (R2 >= 0x0b && R2 <= 0x0e) { snd_ali_detect_spdif_rate()
689 } else if (R2 == 0x12) { snd_ali_detect_spdif_rate()
/linux-4.4.14/drivers/net/wireless/iwlegacy/
H A D4965.c1581 s32 R1, R2, R3; il4965_hw_get_temperature() local
1588 R2 = (s32) le32_to_cpu(il->card_alive_init.therm_r2[1]); il4965_hw_get_temperature()
1594 R2 = (s32) le32_to_cpu(il->card_alive_init.therm_r2[0]); il4965_hw_get_temperature()
1613 D_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt); il4965_hw_get_temperature()
1622 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2); il4965_hw_get_temperature()
H A D4965.h239 * calculation uses 4 measurements, 3 of which (R1, R2, R3) are calibration
254 * degrees Kelvin = ((97 * 259 * (R4 - R2) / (R3 - R1)) / 100) + 8
256 * NOTE: The basic formula is 259 * (R4-R2) / (R3-R1). The 97/100 is
/linux-4.4.14/arch/cris/arch-v10/kernel/
H A Dkgdb.c303 R0, R1, R2, R3, enumerator in enum:register_name
930 " move.d $r2,[cris_reg+0x08] ; Save R2\n"
983 " move.d [cris_reg+0x08],$r2 ; Restore R2\n"
1026 " move.d $r2,[cris_reg+0x08] ; Save R2\n"
1081 " move.d [cris_reg+0x08],$r2 ; Restore R2\n"
/linux-4.4.14/drivers/staging/rtl8188eu/hal/
H A DHal8188ERateAdaptive.c731 ("macid =%d Total =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d D0 =%d valid0 =%x valid1 =%x\n", ODM_RA_TxRPT2Handle_8188E()
754 ("macid =%d R0 =%d R1 =%d R2 =%d R3 =%d R4 =%d drop =%d valid0 =%x RateID =%d SGI =%d\n", ODM_RA_TxRPT2Handle_8188E()
/linux-4.4.14/drivers/mmc/core/
H A Dmmc_ops.c307 * CSD or CID. Native versions of those commands use the R2 type, mmc_send_cxd_data()
702 * CSD or CID. Native versions of those commands use the R2 type, mmc_send_bus_test()
/linux-4.4.14/drivers/tty/serial/
H A Dip22zilog.h40 #define R2 2 macro
H A Dsunzilog.h32 #define R2 2 macro
H A Dzs.h61 #define R2 2 macro
H A Dpmac_zilog.h128 #define R2 2 macro
H A Dip22zilog.c197 /* Don't mess with the interrupt vector (R2, unused by us) and __load_zsregs()
H A Dzs.c277 write_zsreg(zport, R2, regs[2]); load_zsregs()
H A Dsunzilog.c216 /* Don't mess with the interrupt vector (R2, unused by us) and __load_zsregs()
/linux-4.4.14/drivers/media/radio/
H A Dradio-gemtek.c113 #define BU2614_STDF_BITS 3 /* R0..R2, Standard frequency data */
/linux-4.4.14/drivers/net/hamradio/
H A Dz8530.h8 #define R2 2 macro
H A Dscc.c677 vector=InReg(ctrl->chan_B,R2); /* Read the vector */ scc_isr()
1500 wr(scc, R2, chip*16); /* interrupt vector */ z8530_init()
/linux-4.4.14/arch/sh/boards/
H A Dboard-magicpanelr2.c180 * R3 A21; R2 A20; R1 A19; R0 A0; setup_port_multiplexing()
/linux-4.4.14/arch/ia64/kernel/
H A Dunwind_decoder.c182 UNW_DEC_PROLOGUE_GR(R2, rlen, mask, grsave, arg); unw_decode_r2()
/linux-4.4.14/sound/soc/intel/boards/
H A Dcht_bsw_rt5645.c129 {"DMIC R2", NULL, "Int Mic"},
/linux-4.4.14/drivers/input/mouse/
H A Dvsxxxaa.c328 * [0]: 1 0 1 0 R3 R2 R1 R0 vsxxxaa_handle_POR_packet()
/linux-4.4.14/drivers/mfd/
H A Dwm8350-regmap.c29 { 0x007F, 0x0000, 0x0000 }, /* R2 - ROM Mask ID */
H A Dwm8994-regmap.c24 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
256 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
475 { 0x0002, 0x6000 }, /* R2 - Power Management (2) */
/linux-4.4.14/drivers/net/wan/
H A Dz85230.h27 #define R2 2 macro
/linux-4.4.14/fs/sysv/
H A Dsuper.c202 /* All relevant fields are at the same offsets in R2 and R4 */ detect_sysv()
/linux-4.4.14/include/linux/mfd/wm8350/
H A Dcore.h90 * R2 (0x02) - Revision
/linux-4.4.14/arch/mips/
H A DMakefile172 # that GCC might generate R2 code for -march=loongson3a which then is rejected
/linux-4.4.14/arch/hexagon/lib/
H A Dmemcpy.S153 #define len R2 /* length of copy in bytes */
/linux-4.4.14/arch/arm/probes/
H A Ddecode.h252 * instruction will be modified to "AND R0, R2, R3, ASL R1" and then placed into
/linux-4.4.14/arch/arm/kernel/
H A Dentry-header.S60 * xPSR, ReturnAddress(), LR (R14), R12, R3, R2, R1, and R0 are
/linux-4.4.14/include/linux/
H A Dhp_sdc.h255 #define HP_SDC_HIL_ERR 0x81 /* HIL MLC R2 had a bit set */
H A Dhyperv.h163 * 3 . 0 (Windows 8 R2)
/linux-4.4.14/drivers/video/fbdev/
H A Dhyperv_fb.c23 * Server 2012, and 1600x1200 with 16 bit color on Windows Server 2008 R2
/linux-4.4.14/drivers/misc/echo/
H A Decho.c154 R0 *= R2; lms_adapt_bg()
/linux-4.4.14/drivers/net/wireless/rt2x00/
H A Drt2500usb.h613 * R2: TX antenna control
H A Drt2500pci.h980 * R2: TX antenna control
H A Drt61pci.h1107 * R2
H A Drt73usb.h756 * R2
/linux-4.4.14/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-mt8127.h966 "R2", "mt8127",
H A Dpinctrl-mtk-mt8135.h1754 "R2", "mt8135",
/linux-4.4.14/arch/s390/mm/
H A Dfault.c148 pr_cont("R2:%016lx ", *table); dump_pagetable()
/linux-4.4.14/arch/blackfin/include/asm/
H A Ddpmc.h18 #define PM_REG5 R2
/linux-4.4.14/sound/pci/ice1712/
H A Dmaya44.c552 0x02, 0x100, /* R2: headphone L+R muted + update */ wm8776_init()
/linux-4.4.14/drivers/dma/ppc4xx/
H A Dadma.c2317 /* may do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
2322 /* do RXOR R1 R2 R3 */ ppc440spe_dma01_prep_pq()
2326 /* do RXOR R1 R2 R4 */ ppc440spe_dma01_prep_pq()
2329 /* do RXOR R1 R2 R5 */ ppc440spe_dma01_prep_pq()
2333 /* do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
2338 /* do RXOR R1 R2 */ ppc440spe_dma01_prep_pq()
/linux-4.4.14/include/linux/mfd/
H A Dwm8400-audio.h27 * R2 (0x02) - Power Management (1)
/linux-4.4.14/arch/mips/net/
H A Dbpf_jit.c1090 /* R2 and later have the wsbh instruction */ build_body()
/linux-4.4.14/drivers/media/usb/em28xx/
H A Dem28xx-cards.c109 /* Board Hauppauge WinTV HVR 900 (R2) digital */
1197 .name = "Hauppauge WinTV HVR 900 (R2)",
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_ddi.c1228 * Injecting R2 = 2 * R gives: hsw_ddi_calculate_wrpll()
1244 * Injecting R2 = 2 * R and N2 = 2 * N, we get: hsw_ddi_calculate_wrpll()
/linux-4.4.14/drivers/scsi/
H A Dstorvsc_drv.c1248 * If the host is WIN8 or WIN8 R2, claim conformance to SPC-3 storvsc_device_configure()
/linux-4.4.14/sound/usb/
H A Dpcm.c1357 * L1 L2 0x05 R1 R2 0x05 L3 L4 0xfa R3 R4 0xfa fill_playback_urb_dsd_dop()
/linux-4.4.14/drivers/hwmon/
H A Dw83793.c240 * byte 1: Temp R1,R2 mode, each has 1 bit
/linux-4.4.14/net/sctp/
H A Doutqueue.c1551 * R2) Whenever all outstanding data sent to an address have sctp_check_transmitted()
/linux-4.4.14/arch/mips/math-emu/
H A Dcp1emu.c731 /* R2/R6 compatible cop1 instruction. Fall through */ isBranchInstr()
/linux-4.4.14/net/netfilter/
H A Dnf_conntrack_proto_tcp.c81 /* RFC1122 says the R2 limit should be at least 100 seconds.
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dcassini.h1173 #define HP_STATUS1_ACCUR2_MASK 0xE0000000 /* accu R2[6:4] */
1179 #define HP_STATUS2_ACCUR2_MASK 0xF0000000 /* accu R2[3:0] */
/linux-4.4.14/drivers/hid/
H A Dhid-sony.c882 [0x0a] = BTN_TR2, /* R2 */
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dskge.h235 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
H A Dsky2.h465 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
/linux-4.4.14/drivers/base/regmap/
H A Dregmap.c2047 * the data as R1,V1,R2,V2,..,Rn,Vn on the target bus. The target device
/linux-4.4.14/arch/x86/kernel/
H A Dapm_32.c2138 DMI_MATCH(DMI_BIOS_VERSION, "Version R2.08"), },

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