25 	CLI R2;
28 	STI R2;
34 	R2 = IWR_DISABLE_ALL;  define
73 	R2 = IWR_DISABLE_ALL;  define
83 	CLI R2;
97 	P5 = R2;
101 	R2 = IWR_DISABLE_ALL;  define
128 	R2 = 0x0404(Z);  define
129 	R1 = R1|R2;
131 	R2 = DEPOSIT(R7, R1);  define
132 	W[P0] = R2;		/* Set Min Core Voltage */
156 	R2 = IWR_DISABLE_ALL;  define
196 	R2 = [P0];  define
197 	BITSET(R2, 3); /* SRREQ enter self-refresh mode */
198 	[P0] = R2;
201 	R2 = [P0];  define
202 	CC = BITTST(R2, 4);
210 	R2 = [P0];  define
211 	BITSET(R2, 24); /* SRFS enter self-refresh mode */
212 	[P0] = R2;
216 	R2 = w[P1];  define
218 	cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
221 	R2 = [P0];  define
222 	BITCLR(R2, 0); /* SCTLE disable CLKOUT */
223 	[P0] = R2;
234 	R2 = [P0];  define
235 	BITCLR(R2, 3); /* clear SRREQ bit */
236 	[P0] = R2;
242 	R2 = [P0];  define
243 	BITSET(R2, 0); /* SCTLE enable CLKOUT */
244 	[P0] = R2
248 	R2 = [P0];  define
249 	BITCLR(R2, 24); /* clear SRFS bit */
250 	[P0] = R2
264 	[P0 + (SIC_IWR2 - SYSMMR_BASE)] = R2;
301 	R2.H = .Lpm_resume_here;
302 	R2.L = .Lpm_resume_here;
304 	[P0++] = R2;	/* Save Return Address */