| /linux-4.4.14/arch/arm/boot/dts/ |
| D | stih415-clock.dtsi | 59 <&clk_s_a0_pll 0>, /* PLL0 HS */
74 <&clk_s_a0_pll 1>, /* PLL0 LS */
117 <&clk_s_a1_pll 0>, /* PLL0 HS */
132 <&clk_s_a1_pll 1>, /* PLL0 LS */
193 <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
212 <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
231 <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
250 <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
307 <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
326 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
[all …]
|
| D | stih416-clock.dtsi | 60 <&clk_s_a0_pll 0>, /* PLL0 HS */
75 <&clk_s_a0_pll 1>, /* PLL0 LS */
118 <&clk_s_a1_pll 0>, /* PLL0 HS */
133 <&clk_s_a1_pll 1>, /* PLL0 LS */
195 <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
214 <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
233 <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
252 <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
309 <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
328 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
[all …]
|
| /linux-4.4.14/arch/arm/mach-w90x900/ |
| D | clksel.c | 27 #define PLL0 0x00 macro
78 clkval = PLL0; in nuc900_clock_source()
|
| /linux-4.4.14/sound/soc/codecs/ |
| D | ak4642.c | 120 #define PLL0 (1 << 4) macro
121 #define PLL_MASK (PLL3 | PLL2 | PLL1 | PLL0)
352 pll = PLL2 | PLL0; in ak4642_dai_set_sysclk()
358 pll = PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
364 pll = PLL3 | PLL2 | PLL0; in ak4642_dai_set_sysclk()
375 pll = PLL3 | PLL2 | PLL1 | PLL0; in ak4642_dai_set_sysclk()
|
| /linux-4.4.14/drivers/media/dvb-frontends/ |
| D | zl10039.c | 53 PLL0 = 0, enumerator
231 ret = zl10039_write(state, PLL0, buf, sizeof(buf)); in zl10039_set_params()
|
| /linux-4.4.14/Documentation/devicetree/bindings/clock/st/ |
| D | st,clkgen-divmux.txt | 36 <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
|
| D | st,flexgen.txt | 21 | | |PLL0 | | | | |Dividers| |Dividers| | |
|
| /linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/ |
| D | qcom,gcc-msm8660.h | 264 #define PLL0 247 macro
|
| D | qcom,gcc-ipq806x.h | 237 #define PLL0 220 macro
|
| D | qcom,gcc-msm8960.h | 292 #define PLL0 276 macro
|
| /linux-4.4.14/arch/avr32/mach-at32ap/ |
| D | clock.c | 270 seq_printf(s, "PLL0 = %8x\n", pm_readl(PLL0)); in clk_show()
|
| D | at32ap700x.c | 198 control = pm_readl(PLL0); in pll0_get_rate()
2274 if (pm_readl(PLL0) & PM_BIT(PLLOSC)) in setup_platform()
|
| /linux-4.4.14/drivers/clk/qcom/ |
| D | gcc-ipq806x.c | 2723 [PLL0] = &pll0.clkr,
|