Searched refs:PIPE_A (Results 1 - 19 of 19) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_ddi.c621 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | hsw_fdi_link_train()
629 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); hsw_fdi_link_train()
630 POSTING_READ(FDI_RX_CTL(PIPE_A)); hsw_fdi_link_train()
635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); hsw_fdi_link_train()
664 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); hsw_fdi_link_train()
668 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); hsw_fdi_link_train()
669 POSTING_READ(FDI_RX_CTL(PIPE_A)); hsw_fdi_link_train()
675 temp = I915_READ(FDI_RX_MISC(PIPE_A)); hsw_fdi_link_train()
677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); hsw_fdi_link_train()
678 POSTING_READ(FDI_RX_MISC(PIPE_A)); hsw_fdi_link_train()
712 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); hsw_fdi_link_train()
713 POSTING_READ(FDI_RX_CTL(PIPE_A)); hsw_fdi_link_train()
716 temp = I915_READ(FDI_RX_MISC(PIPE_A)); hsw_fdi_link_train()
719 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); hsw_fdi_link_train()
720 POSTING_READ(FDI_RX_MISC(PIPE_A)); hsw_fdi_link_train()
1890 case PIPE_A: intel_ddi_enable_transcoder_func()
2035 *pipe = PIPE_A; intel_ddi_get_hw_state()
3092 val = I915_READ(FDI_RX_CTL(PIPE_A)); intel_ddi_fdi_disable()
3094 I915_WRITE(FDI_RX_CTL(PIPE_A), val); intel_ddi_fdi_disable()
3096 val = I915_READ(FDI_RX_MISC(PIPE_A)); intel_ddi_fdi_disable()
3099 I915_WRITE(FDI_RX_MISC(PIPE_A), val); intel_ddi_fdi_disable()
3101 val = I915_READ(FDI_RX_CTL(PIPE_A)); intel_ddi_fdi_disable()
3103 I915_WRITE(FDI_RX_CTL(PIPE_A), val); intel_ddi_fdi_disable()
3105 val = I915_READ(FDI_RX_CTL(PIPE_A)); intel_ddi_fdi_disable()
3107 I915_WRITE(FDI_RX_CTL(PIPE_A), val); intel_ddi_fdi_disable()
H A Dintel_pm.c344 case PIPE_A: vlv_get_fifo_size()
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); vlv_write_wm_values()
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | vlv_write_wm_values()
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | vlv_write_wm_values()
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); vlv_write_wm_values()
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | vlv_write_wm_values()
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | vlv_write_wm_values()
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); vlv_write_wm_values()
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | vlv_write_wm_values()
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | vlv_write_wm_values()
875 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); vlv_write_wm_values()
1197 case PIPE_A:
1366 if (g4x_compute_wm0(dev, PIPE_A, g4x_update_wm()
1370 enabled |= 1 << PIPE_A; g4x_update_wm()
2681 if (dirty & WM_DIRTY_PIPE(PIPE_A)) ilk_write_wm_values()
2688 if (dirty & WM_DIRTY_LINETIME(PIPE_A)) ilk_write_wm_values()
2689 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); ilk_write_wm_values()
3874 [PIPE_A] = WM0_PIPEA_ILK, ilk_pipe_wm_get_hw_state()
3942 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3945 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3946 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3947 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3973 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3974 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3975 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3986 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3987 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3988 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
6566 I915_WRITE(TRANS_CHICKEN1(PIPE_A), lpt_init_clock_gating()
6567 I915_READ(TRANS_CHICKEN1(PIPE_A)) | lpt_init_clock_gating()
H A Dintel_runtime_pm.c251 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); skl_power_well_post_enable()
880 if (pipe != PIPE_A) vlv_display_power_well_init()
1106 pipe = PIPE_A; chv_dpio_cmn_power_well_enable()
1165 assert_pll_disabled(dev_priv, PIPE_A); chv_dpio_cmn_power_well_disable()
1189 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; assert_chv_phy_powergate()
1375 WARN_ON_ONCE(power_well->data != PIPE_A); chv_pipe_power_well_sync_hw()
1383 WARN_ON_ONCE(power_well->data != PIPE_A); chv_pipe_power_well_enable()
1393 WARN_ON_ONCE(power_well->data != PIPE_A); chv_pipe_power_well_disable()
1715 .data = PIPE_A,
1954 uint32_t status = I915_READ(DPLL(PIPE_A)); chv_phy_control_init()
H A Dintel_dp_mst.c451 for (i = PIPE_A; i <= PIPE_C; i++) { intel_dp_add_mst_connector()
561 for (i = PIPE_A; i <= PIPE_C; i++) intel_dp_create_fake_mst_encoders()
H A Dintel_panel.c522 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) _vlv_get_backlight()
627 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) vlv_set_backlight()
792 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) vlv_disable_backlight()
1021 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) vlv_enable_backlight()
1578 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) vlv_setup_backlight()
H A Di915_irq.c600 i915_enable_pipestat(dev_priv, PIPE_A, i915_enable_asle_pipestat()
1643 case PIPE_A: for_each_pipe()
3210 if (pipe_mask & 1 << PIPE_A) gen8_irq_power_well_post_enable()
3211 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, gen8_irq_power_well_post_enable()
3212 dev_priv->de_irq_mask[PIPE_A], gen8_irq_power_well_post_enable()
3213 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); gen8_irq_power_well_post_enable()
3476 POSTING_READ(PIPESTAT(PIPE_A)); valleyview_display_irqs_install()
3481 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); valleyview_display_irqs_install()
3521 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); valleyview_display_irqs_uninstall()
3530 POSTING_READ(PIPESTAT(PIPE_A)); valleyview_display_irqs_uninstall()
3657 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked; gen8_de_irq_postinstall()
3807 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); i8xx_irq_postinstall()
3989 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); i915_irq_postinstall()
4191 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); i965_irq_postinstall()
4192 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS); i965_irq_postinstall()
H A Dintel_fifo_underrun.c144 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : ironlake_set_fifo_underrun_reporting()
H A Di915_debugfs.c2680 return "PIPE_A"; power_domain_str()
2924 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; cursor_active()
3447 .pipe = PIPE_A,
3639 case PIPE_A: vlv_pipe_crc_ctl_reg()
3722 if (pipe == PIPE_A) i9xx_pipe_crc_ctl_reg()
3740 case PIPE_A: vlv_undo_pipe_scramble_reset()
3764 if (pipe == PIPE_A) g4x_undo_pipe_scramble_reset()
3806 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); hsw_trans_edp_pipe_A_crc_wa()
3854 if (IS_HASWELL(dev) && pipe == PIPE_A) ivb_pipe_crc_ctl_reg()
3966 else if (IS_HASWELL(dev) && pipe == PIPE_A) pipe_crc_set_source()
H A Dintel_dsi.c686 *pipe = port == PORT_A ? PIPE_A : PIPE_B; intel_dsi_get_hw_state()
1171 intel_encoder->crtc_mask = (1 << PIPE_A); intel_dsi_init()
H A Dintel_display.c1291 enum pipe panel_pipe = PIPE_A; assert_panel_unlocked()
1334 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; assert_cursor()
1353 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || assert_pipe()
1775 I915_WRITE(DPLL(PIPE_A), i9xx_disable_pll()
1776 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); i9xx_disable_pll()
1780 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || i9xx_disable_pll()
1821 if (pipe != PIPE_A) chv_disable_pll()
2033 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); lpt_enable_pch_transcoder()
2035 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); lpt_enable_pch_transcoder()
2093 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); lpt_disable_pch_transcoder()
2095 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); lpt_disable_pch_transcoder()
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || intel_enable_pipe()
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && intel_disable_pipe()
4120 case PIPE_A: ivybridge_update_fdi_bc_bifurcation()
4245 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); lpt_pch_enable()
4963 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; hsw_crtc_supports_ips()
6525 case PIPE_A: ironlake_check_fdi_lanes()
6663 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && intel_crtc_compute_config()
7389 if (pipe == PIPE_A) vlv_prepare_pll()
7397 if (pipe == PIPE_A) vlv_prepare_pll()
7422 if (crtc->pipe != PIPE_A) chv_compute_dpll()
7838 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || i9xx_set_pipeconf()
9839 tmp = I915_READ(FDI_RX_CTL(PIPE_A)); haswell_get_ddi_port_state()
9870 trans_edp_pipe = PIPE_A; haswell_get_pipe_config()
9968 I915_WRITE(CURCNTR(PIPE_A), 0); i845_update_cursor()
9969 POSTING_READ(CURCNTR(PIPE_A)); i845_update_cursor()
9974 I915_WRITE(CURBASE(PIPE_A), base); i845_update_cursor()
9984 I915_WRITE(CURCNTR(PIPE_A), cntl); i845_update_cursor()
9985 POSTING_READ(CURCNTR(PIPE_A)); i845_update_cursor()
12778 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || for_each_crtc_in_state()
15099 crtc->pipe == PIPE_A && !crtc->active) {
H A Dintel_crt.c876 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; intel_crt_init()
H A Dintel_dp.c377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); vlv_power_sequencer_pipe()
410 pipe = PIPE_A; vlv_power_sequencer_pipe()
462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { vlv_initial_pps_pipe()
2677 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) vlv_steal_power_sequencer()
5972 if (pipe != PIPE_A && pipe != PIPE_B) intel_edp_init_connector()
5975 if (pipe != PIPE_A && pipe != PIPE_B) intel_edp_init_connector()
5976 pipe = PIPE_A; intel_edp_init_connector()
H A Di915_cmd_parser.c485 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
H A Di915_dma.c780 info->num_sprites[PIPE_A] = 2; intel_device_info_runtime_init()
H A Dintel_drv.h843 case PIPE_A: vlv_pipe_to_channel()
H A Di915_reg.h32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
4465 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4907 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
H A Di915_drv.h116 PIPE_A = 0, enumerator in enum:pipe
/linux-4.4.14/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c476 /* keep old default behaviour - prefer PIPE_A */ intelfbhw_active_pipe()
480 if (unlikely(pipe == PIPE_A)) intelfbhw_active_pipe()
481 return PIPE_A; intelfbhw_active_pipe()
486 if (likely(pipe == PIPE_A)) intelfbhw_active_pipe()
487 return PIPE_A; intelfbhw_active_pipe()
489 /* Impossible that no pipe is selected - return PIPE_A */ intelfbhw_active_pipe()
492 pipe = PIPE_A; intelfbhw_active_pipe()
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? intelfbhw_setcolreg()
H A Dintelfbhw.h182 #define PIPE_A 0 macro

Completed in 1398 milliseconds