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Searched refs:PIPE_A (Results 1 – 19 of 19) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_ddi.c621 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) | in hsw_fdi_link_train()
629 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
630 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
635 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
664 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64)); in hsw_fdi_link_train()
668 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val); in hsw_fdi_link_train()
669 POSTING_READ(FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
675 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
677 I915_WRITE(FDI_RX_MISC(PIPE_A), temp); in hsw_fdi_link_train()
678 POSTING_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
Dintel_runtime_pm.c251 gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); in skl_power_well_post_enable()
880 if (pipe != PIPE_A) in vlv_display_power_well_init()
1106 pipe = PIPE_A; in chv_dpio_cmn_power_well_enable()
1165 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1189 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; in assert_chv_phy_powergate()
1375 WARN_ON_ONCE(power_well->data != PIPE_A); in chv_pipe_power_well_sync_hw()
1383 WARN_ON_ONCE(power_well->data != PIPE_A); in chv_pipe_power_well_enable()
1393 WARN_ON_ONCE(power_well->data != PIPE_A); in chv_pipe_power_well_disable()
1715 .data = PIPE_A,
1954 uint32_t status = I915_READ(DPLL(PIPE_A)); in chv_phy_control_init()
Dintel_pm.c344 case PIPE_A: in vlv_get_fifo_size()
835 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); in vlv_write_wm_values()
837 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | in vlv_write_wm_values()
838 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | in vlv_write_wm_values()
839 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); in vlv_write_wm_values()
861 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
862 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
863 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); in vlv_write_wm_values()
873 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
874 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
[all …]
Di915_irq.c600 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
1643 case PIPE_A: in valleyview_pipestat_irq_handler()
3210 if (pipe_mask & 1 << PIPE_A) in gen8_irq_power_well_post_enable()
3211 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A, in gen8_irq_power_well_post_enable()
3212 dev_priv->de_irq_mask[PIPE_A], in gen8_irq_power_well_post_enable()
3213 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier); in gen8_irq_power_well_post_enable()
3476 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_install()
3481 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_install()
3521 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in valleyview_display_irqs_uninstall()
3530 POSTING_READ(PIPESTAT(PIPE_A)); in valleyview_display_irqs_uninstall()
[all …]
Dintel_dp_mst.c451 for (i = PIPE_A; i <= PIPE_C; i++) { in intel_dp_add_mst_connector()
561 for (i = PIPE_A; i <= PIPE_C; i++) in intel_dp_create_fake_mst_encoders()
Dintel_fifo_underrun.c144 uint32_t bit = (pipe == PIPE_A) ? DE_PIPEA_FIFO_UNDERRUN : in ironlake_set_fifo_underrun_reporting()
Dintel_panel.c522 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
627 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_set_backlight()
792 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_disable_backlight()
1021 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_enable_backlight()
1578 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Dintel_display.c1291 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()
1334 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; in assert_cursor()
1353 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in assert_pipe()
1775 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
1776 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1780 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || in i9xx_disable_pll()
1821 if (pipe != PIPE_A) in chv_disable_pll()
2033 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
2035 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
2093 val = I915_READ(TRANS_CHICKEN2(PIPE_A)); in lpt_disable_pch_transcoder()
[all …]
Di915_debugfs.c2924 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; in cursor_active()
3447 .pipe = PIPE_A,
3639 case PIPE_A: in vlv_pipe_crc_ctl_reg()
3722 if (pipe == PIPE_A) in i9xx_pipe_crc_ctl_reg()
3740 case PIPE_A: in vlv_undo_pipe_scramble_reset()
3764 if (pipe == PIPE_A) in g4x_undo_pipe_scramble_reset()
3806 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]); in hsw_trans_edp_pipe_A_crc_wa()
3854 if (IS_HASWELL(dev) && pipe == PIPE_A) in ivb_pipe_crc_ctl_reg()
3966 else if (IS_HASWELL(dev) && pipe == PIPE_A) in pipe_crc_set_source()
Dintel_dsi.c686 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1171 intel_encoder->crtc_mask = (1 << PIPE_A); in intel_dsi_init()
Dintel_dp.c377 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_power_sequencer_pipe()
410 pipe = PIPE_A; in vlv_power_sequencer_pipe()
462 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
2677 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_steal_power_sequencer()
5972 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
5975 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
5976 pipe = PIPE_A; in intel_edp_init_connector()
Dintel_crt.c876 dev_priv->fdi_rx_config = I915_READ(FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
Di915_cmd_parser.c485 REG32(GEN7_PIPE_DE_LOAD_SL(PIPE_A)),
Di915_dma.c780 info->num_sprites[PIPE_A] = 2; in intel_device_info_runtime_init()
Dintel_drv.h843 case PIPE_A: in vlv_pipe_to_channel()
Di915_reg.h32 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
4465 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
4907 dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
Di915_drv.h116 PIPE_A = 0, enumerator
/linux-4.4.14/drivers/video/fbdev/intelfb/
Dintelfbhw.c480 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
481 return PIPE_A; in intelfbhw_active_pipe()
486 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
487 return PIPE_A; in intelfbhw_active_pipe()
492 pipe = PIPE_A; in intelfbhw_active_pipe()
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro