Searched refs:PCLK_UART1 (Results 1 - 64 of 64) sorted by relevance

/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Ds3c2410.h35 #define PCLK_UART1 17 macro
H A Ds3c2412.h52 #define PCLK_UART1 40 macro
H A Ds3c2443.h70 #define PCLK_UART1 73 macro
H A Dexynos7-clk.h96 #define PCLK_UART1 1 macro
H A Dsamsung,s3c64xx-clock.h90 #define PCLK_UART1 72 macro
H A Drk3188-cru-common.h89 #define PCLK_UART1 333 macro
H A Drk3288-cru.h140 #define PCLK_UART1 342 macro
H A Drk3368-cru.h129 #define PCLK_UART1 342 macro
/linux-4.4.14/drivers/clk/samsung/
H A Dclk-s3c2410.c127 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
220 ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
223 ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
308 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
311 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
H A Dclk-s3c2412.c162 GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
186 ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
189 ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
H A Dclk-s3c2443.c187 GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
195 ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
199 ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
H A Dclk-s3c64xx.c309 GATE_BUS(PCLK_UART1, "pclk_uart1", "pclk", PCLK_GATE, 2),
414 ALIAS(PCLK_UART1, "s3c6400-uart.1", "uart"),
H A Dclk-exynos7.c753 GATE(PCLK_UART1, "pclk_uart1", "mout_aclk_peric1_66_user",
/linux-4.4.14/drivers/clk/rockchip/
H A Dclk-rk3188.c623 GATE(PCLK_UART1, "pclk_uart1", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
710 GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
H A Dclk-rk3368.c773 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 8, GFLAGS),
H A Dclk-rk3288.c696 GATE(PCLK_UART1, "pclk_uart1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 9, GFLAGS),

Completed in 353 milliseconds