1/* 2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 16#define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 17 18/* core clocks */ 19#define PLL_APLLB 1 20#define PLL_APLLL 2 21#define PLL_DPLL 3 22#define PLL_CPLL 4 23#define PLL_GPLL 5 24#define PLL_NPLL 6 25#define ARMCLKB 7 26#define ARMCLKL 8 27 28/* sclk gates (special clocks) */ 29#define SCLK_GPU_CORE 64 30#define SCLK_SPI0 65 31#define SCLK_SPI1 66 32#define SCLK_SPI2 67 33#define SCLK_SDMMC 68 34#define SCLK_SDIO0 69 35#define SCLK_EMMC 71 36#define SCLK_TSADC 72 37#define SCLK_SARADC 73 38#define SCLK_NANDC0 75 39#define SCLK_UART0 77 40#define SCLK_UART1 78 41#define SCLK_UART2 79 42#define SCLK_UART3 80 43#define SCLK_UART4 81 44#define SCLK_I2S_8CH 82 45#define SCLK_SPDIF_8CH 83 46#define SCLK_I2S_2CH 84 47#define SCLK_TIMER0 85 48#define SCLK_TIMER1 86 49#define SCLK_TIMER2 87 50#define SCLK_TIMER3 88 51#define SCLK_TIMER4 89 52#define SCLK_TIMER5 90 53#define SCLK_TIMER6 91 54#define SCLK_OTGPHY0 93 55#define SCLK_OTG_ADP 96 56#define SCLK_HSICPHY480M 97 57#define SCLK_HSICPHY12M 98 58#define SCLK_MACREF 99 59#define SCLK_VOP0_PWM 100 60#define SCLK_MAC_RX 102 61#define SCLK_MAC_TX 103 62#define SCLK_EDP_24M 104 63#define SCLK_EDP 105 64#define SCLK_RGA 106 65#define SCLK_ISP 107 66#define SCLK_HDCP 108 67#define SCLK_HDMI_HDCP 109 68#define SCLK_HDMI_CEC 110 69#define SCLK_HEVC_CABAC 111 70#define SCLK_HEVC_CORE 112 71#define SCLK_I2S_8CH_OUT 113 72#define SCLK_SDMMC_DRV 114 73#define SCLK_SDIO0_DRV 115 74#define SCLK_EMMC_DRV 117 75#define SCLK_SDMMC_SAMPLE 118 76#define SCLK_SDIO0_SAMPLE 119 77#define SCLK_EMMC_SAMPLE 121 78#define SCLK_USBPHY480M 122 79#define SCLK_PVTM_CORE 123 80#define SCLK_PVTM_GPU 124 81#define SCLK_PVTM_PMU 125 82#define SCLK_SFC 126 83#define SCLK_MAC 127 84#define SCLK_MACREF_OUT 128 85 86#define DCLK_VOP 190 87#define MCLK_CRYPTO 191 88 89/* aclk gates */ 90#define ACLK_GPU_MEM 192 91#define ACLK_GPU_CFG 193 92#define ACLK_DMAC_BUS 194 93#define ACLK_DMAC_PERI 195 94#define ACLK_PERI_MMU 196 95#define ACLK_GMAC 197 96#define ACLK_VOP 198 97#define ACLK_VOP_IEP 199 98#define ACLK_RGA 200 99#define ACLK_HDCP 201 100#define ACLK_IEP 202 101#define ACLK_VIO0_NOC 203 102#define ACLK_VIP 204 103#define ACLK_ISP 205 104#define ACLK_VIO1_NOC 206 105#define ACLK_VIDEO 208 106#define ACLK_BUS 209 107#define ACLK_PERI 210 108 109/* pclk gates */ 110#define PCLK_GPIO0 320 111#define PCLK_GPIO1 321 112#define PCLK_GPIO2 322 113#define PCLK_GPIO3 323 114#define PCLK_PMUGRF 324 115#define PCLK_MAILBOX 325 116#define PCLK_GRF 329 117#define PCLK_SGRF 330 118#define PCLK_PMU 331 119#define PCLK_I2C0 332 120#define PCLK_I2C1 333 121#define PCLK_I2C2 334 122#define PCLK_I2C3 335 123#define PCLK_I2C4 336 124#define PCLK_I2C5 337 125#define PCLK_SPI0 338 126#define PCLK_SPI1 339 127#define PCLK_SPI2 340 128#define PCLK_UART0 341 129#define PCLK_UART1 342 130#define PCLK_UART2 343 131#define PCLK_UART3 344 132#define PCLK_UART4 345 133#define PCLK_TSADC 346 134#define PCLK_SARADC 347 135#define PCLK_SIM 348 136#define PCLK_GMAC 349 137#define PCLK_PWM0 350 138#define PCLK_PWM1 351 139#define PCLK_TIMER0 353 140#define PCLK_TIMER1 354 141#define PCLK_EDP_CTRL 355 142#define PCLK_MIPI_DSI0 356 143#define PCLK_MIPI_CSI 358 144#define PCLK_HDCP 359 145#define PCLK_HDMI_CTRL 360 146#define PCLK_VIO_H2P 361 147#define PCLK_BUS 362 148#define PCLK_PERI 363 149#define PCLK_DDRUPCTL 364 150#define PCLK_DDRPHY 365 151#define PCLK_ISP 366 152#define PCLK_VIP 367 153#define PCLK_WDT 368 154 155/* hclk gates */ 156#define HCLK_SFC 448 157#define HCLK_OTG0 449 158#define HCLK_HOST0 450 159#define HCLK_HOST1 451 160#define HCLK_HSIC 452 161#define HCLK_NANDC0 453 162#define HCLK_TSP 455 163#define HCLK_SDMMC 456 164#define HCLK_SDIO0 457 165#define HCLK_EMMC 459 166#define HCLK_HSADC 460 167#define HCLK_CRYPTO 461 168#define HCLK_I2S_2CH 462 169#define HCLK_I2S_8CH 463 170#define HCLK_SPDIF 464 171#define HCLK_VOP 465 172#define HCLK_ROM 467 173#define HCLK_IEP 468 174#define HCLK_ISP 469 175#define HCLK_RGA 470 176#define HCLK_VIO_AHB_ARBI 471 177#define HCLK_VIO_NOC 472 178#define HCLK_VIP 473 179#define HCLK_VIO_H2P 474 180#define HCLK_VIO_HDCPMMU 475 181#define HCLK_VIDEO 476 182#define HCLK_BUS 477 183#define HCLK_PERI 478 184 185#define CLK_NR_CLKS (HCLK_PERI + 1) 186 187/* soft-reset indices */ 188#define SRST_CORE_B0 0 189#define SRST_CORE_B1 1 190#define SRST_CORE_B2 2 191#define SRST_CORE_B3 3 192#define SRST_CORE_B0_PO 4 193#define SRST_CORE_B1_PO 5 194#define SRST_CORE_B2_PO 6 195#define SRST_CORE_B3_PO 7 196#define SRST_L2_B 8 197#define SRST_ADB_B 9 198#define SRST_PD_CORE_B_NIU 10 199#define SRST_PDBUS_STRSYS 11 200#define SRST_SOCDBG_B 14 201#define SRST_CORE_B_DBG 15 202 203#define SRST_DMAC1 18 204#define SRST_INTMEM 19 205#define SRST_ROM 20 206#define SRST_SPDIF8CH 21 207#define SRST_I2S8CH 23 208#define SRST_MAILBOX 24 209#define SRST_I2S2CH 25 210#define SRST_EFUSE_256 26 211#define SRST_MCU_SYS 28 212#define SRST_MCU_PO 29 213#define SRST_MCU_NOC 30 214#define SRST_EFUSE 31 215 216#define SRST_GPIO0 32 217#define SRST_GPIO1 33 218#define SRST_GPIO2 34 219#define SRST_GPIO3 35 220#define SRST_GPIO4 36 221#define SRST_PMUGRF 41 222#define SRST_I2C0 42 223#define SRST_I2C1 43 224#define SRST_I2C2 44 225#define SRST_I2C3 45 226#define SRST_I2C4 46 227#define SRST_I2C5 47 228 229#define SRST_DWPWM 48 230#define SRST_MMC_PERI 49 231#define SRST_PERIPH_MMU 50 232#define SRST_GRF 55 233#define SRST_PMU 56 234#define SRST_PERIPH_AXI 57 235#define SRST_PERIPH_AHB 58 236#define SRST_PERIPH_APB 59 237#define SRST_PERIPH_NIU 60 238#define SRST_PDPERI_AHB_ARBI 61 239#define SRST_EMEM 62 240#define SRST_USB_PERI 63 241 242#define SRST_DMAC2 64 243#define SRST_MAC 66 244#define SRST_GPS 67 245#define SRST_RKPWM 69 246#define SRST_USBHOST0 72 247#define SRST_HSIC 73 248#define SRST_HSIC_AUX 74 249#define SRST_HSIC_PHY 75 250#define SRST_HSADC 76 251#define SRST_NANDC0 77 252#define SRST_SFC 79 253 254#define SRST_SPI0 83 255#define SRST_SPI1 84 256#define SRST_SPI2 85 257#define SRST_SARADC 87 258#define SRST_PDALIVE_NIU 88 259#define SRST_PDPMU_INTMEM 89 260#define SRST_PDPMU_NIU 90 261#define SRST_SGRF 91 262 263#define SRST_VIO_ARBI 96 264#define SRST_RGA_NIU 97 265#define SRST_VIO0_NIU_AXI 98 266#define SRST_VIO_NIU_AHB 99 267#define SRST_LCDC0_AXI 100 268#define SRST_LCDC0_AHB 101 269#define SRST_LCDC0_DCLK 102 270#define SRST_VIP 104 271#define SRST_RGA_CORE 105 272#define SRST_IEP_AXI 106 273#define SRST_IEP_AHB 107 274#define SRST_RGA_AXI 108 275#define SRST_RGA_AHB 109 276#define SRST_ISP 110 277#define SRST_EDP_24M 111 278 279#define SRST_VIDEO_AXI 112 280#define SRST_VIDEO_AHB 113 281#define SRST_MIPIDPHYTX 114 282#define SRST_MIPIDSI0 115 283#define SRST_MIPIDPHYRX 116 284#define SRST_MIPICSI 117 285#define SRST_GPU 120 286#define SRST_HDMI 121 287#define SRST_EDP 122 288#define SRST_PMU_PVTM 123 289#define SRST_CORE_PVTM 124 290#define SRST_GPU_PVTM 125 291#define SRST_GPU_SYS 126 292#define SRST_GPU_MEM_NIU 127 293 294#define SRST_MMC0 128 295#define SRST_SDIO0 129 296#define SRST_EMMC 131 297#define SRST_USBOTG_AHB 132 298#define SRST_USBOTG_PHY 133 299#define SRST_USBOTG_CON 134 300#define SRST_USBHOST0_AHB 135 301#define SRST_USBHOST0_PHY 136 302#define SRST_USBHOST0_CON 137 303#define SRST_USBOTG_UTMI 138 304#define SRST_USBHOST1_UTMI 139 305#define SRST_USB_ADP 141 306 307#define SRST_CORESIGHT 144 308#define SRST_PD_CORE_AHB_NOC 145 309#define SRST_PD_CORE_APB_NOC 146 310#define SRST_GIC 148 311#define SRST_LCDC_PWM0 149 312#define SRST_RGA_H2P_BRG 153 313#define SRST_VIDEO 154 314#define SRST_GPU_CFG_NIU 157 315#define SRST_TSADC 159 316 317#define SRST_DDRPHY0 160 318#define SRST_DDRPHY0_APB 161 319#define SRST_DDRCTRL0 162 320#define SRST_DDRCTRL0_APB 163 321#define SRST_VIDEO_NIU 165 322#define SRST_VIDEO_NIU_AHB 167 323#define SRST_DDRMSCH0 170 324#define SRST_PDBUS_AHB 173 325#define SRST_CRYPTO 174 326 327#define SRST_UART0 179 328#define SRST_UART1 180 329#define SRST_UART2 181 330#define SRST_UART3 182 331#define SRST_UART4 183 332#define SRST_SIMC 186 333#define SRST_TSP 188 334#define SRST_TSP_CLKIN0 189 335 336#define SRST_CORE_L0 192 337#define SRST_CORE_L1 193 338#define SRST_CORE_L2 194 339#define SRST_CORE_L3 195 340#define SRST_CORE_L0_PO 195 341#define SRST_CORE_L1_PO 197 342#define SRST_CORE_L2_PO 198 343#define SRST_CORE_L3_PO 199 344#define SRST_L2_L 200 345#define SRST_ADB_L 201 346#define SRST_PD_CORE_L_NIU 202 347#define SRST_CCI_SYS 203 348#define SRST_CCI_DDR 204 349#define SRST_CCI 205 350#define SRST_SOCDBG_L 206 351#define SRST_CORE_L_DBG 207 352 353#define SRST_CORE_B0_NC 208 354#define SRST_CORE_B0_PO_NC 209 355#define SRST_L2_B_NC 210 356#define SRST_ADB_B_NC 211 357#define SRST_PD_CORE_B_NIU_NC 212 358#define SRST_PDBUS_STRSYS_NC 213 359#define SRST_CORE_L0_NC 214 360#define SRST_CORE_L0_PO_NC 215 361#define SRST_L2_L_NC 216 362#define SRST_ADB_L_NC 217 363#define SRST_PD_CORE_L_NIU_NC 218 364#define SRST_CCI_SYS_NC 219 365#define SRST_CCI_DDR_NC 220 366#define SRST_CCI_NC 221 367#define SRST_TRACE_NC 222 368 369#define SRST_TIMER00 224 370#define SRST_TIMER01 225 371#define SRST_TIMER02 226 372#define SRST_TIMER03 227 373#define SRST_TIMER04 228 374#define SRST_TIMER05 229 375#define SRST_TIMER10 230 376#define SRST_TIMER11 231 377#define SRST_TIMER12 232 378#define SRST_TIMER13 233 379#define SRST_TIMER14 234 380#define SRST_TIMER15 235 381#define SRST_TIMER0_APB 236 382#define SRST_TIMER1_APB 237 383 384#endif 385