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Searched refs:MT76_SET (Results 1 – 9 of 9) sorted by relevance

/linux-4.4.14/drivers/net/wireless/mediatek/mt7601u/
Ddma.h82 MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) | in mt7601u_dma_skb_wrap()
83 MT76_SET(MT_TXD_INFO_D_PORT, d_port) | in mt7601u_dma_skb_wrap()
84 MT76_SET(MT_TXD_INFO_TYPE, type); in mt7601u_dma_skb_wrap()
93 flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel); in mt7601u_dma_skb_wrap_pkt()
Dtx.c178 txwi->ack_ctl |= MT76_SET(MT_TXWI_ACK_CTL_BA_WINDOW, ba_size); in mt7601u_push_txwi()
181 MT76_SET(MT_TXWI_FLAGS_MPDU_DENSITY, in mt7601u_push_txwi()
191 pkt_len |= MT76_SET(MT_TXWI_LEN_PKTID, pkt_id); in mt7601u_push_txwi()
288 val = MT76_SET(MT_EDCA_CFG_AIFSN, params->aifs) | in mt7601u_conf_tx()
289 MT76_SET(MT_EDCA_CFG_CWMIN, cw_min) | in mt7601u_conf_tx()
290 MT76_SET(MT_EDCA_CFG_CWMAX, cw_max); in mt7601u_conf_tx()
298 val |= MT76_SET(MT_EDCA_CFG_TXOP, params->txop); in mt7601u_conf_tx()
Dmac.c128 rateval = MT76_SET(MT_RXWI_RATE_MCS, rate_idx); in mt76_mac_tx_rate_val()
129 rateval |= MT76_SET(MT_RXWI_RATE_PHY, phy); in mt76_mac_tx_rate_val()
130 rateval |= MT76_SET(MT_RXWI_RATE_BW, bw); in mt76_mac_tx_rate_val()
273 val |= MT76_SET(MT_BEACON_TIME_CFG_INTVAL, interval << 4) | in mt7601u_mac_config_tsf()
352 attr = MT76_SET(MT_WCID_ATTR_BSS_IDX, vif_idx & 7) | in mt7601u_mac_wcid_setup()
353 MT76_SET(MT_WCID_ATTR_BSS_IDX_EXT, !!(vif_idx & 8)); in mt7601u_mac_wcid_setup()
385 MT76_SET(MT_MAX_LEN_CFG_AMPDU, min_factor)); in mt7601u_mac_set_ampdu_factor()
545 val |= MT76_SET(MT_WCID_ATTR_PKEY_MODE, cipher & 7) | in mt76_mac_wcid_set_key()
546 MT76_SET(MT_WCID_ATTR_PKEY_MODE_EXT, cipher >> 3); in mt76_mac_wcid_set_key()
Dmcu.c46 MT76_SET(MT_TXD_CMD_INFO_SEQ, seq) | in mt7601u_dma_skb_wrap_cmd()
47 MT76_SET(MT_TXD_CMD_INFO_TYPE, cmd))); in mt7601u_dma_skb_wrap_cmd()
294 reg = cpu_to_le32(MT76_SET(MT_TXD_INFO_TYPE, DMA_PACKET) | in __mt7601u_dma_fw()
295 MT76_SET(MT_TXD_INFO_D_PORT, CPU_TX_PORT) | in __mt7601u_dma_fw()
296 MT76_SET(MT_TXD_INFO_LEN, len)); in __mt7601u_dma_fw()
Dutil.h65 #define MT76_SET(_mask, _val) \ macro
Dinit.c111 val = MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) | in mt7601u_init_usb_dma()
112 MT76_SET(MT_USB_DMA_CFG_RX_BULK_AGG_LMT, MT_USB_AGGR_SIZE_LIMIT) | in mt7601u_init_usb_dma()
399 mt7601u_wr(dev, MT_TXOP_CTRL_CFG, MT76_SET(MT_TXOP_TRUN_EN, 0x3f) | in mt7601u_init_hardware()
400 MT76_SET(MT_TXOP_EXT_CCA_DLY, 0x58)); in mt7601u_init_hardware()
Dphy.c44 mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_DATA, value) | in mt7601u_rf_wr()
45 MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | in mt7601u_rf_wr()
46 MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | in mt7601u_rf_wr()
77 mt7601u_wr(dev, MT_RF_CSR_CFG, MT76_SET(MT_RF_CSR_CFG_REG_BANK, bank) | in mt7601u_rf_rr()
78 MT76_SET(MT_RF_CSR_CFG_REG_ID, offset) | in mt7601u_rf_rr()
142 MT76_SET(MT_BBP_CSR_CFG_VAL, val) | in mt7601u_bbp_wr()
143 MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | in mt7601u_bbp_wr()
166 MT76_SET(MT_BBP_CSR_CFG_REG_NUM, offset) | in mt7601u_bbp_rr()
Deeprom.c48 val |= MT76_SET(MT_EFUSE_CTRL_AIN, addr & ~0xf) | in mt7601u_efuse_read()
49 MT76_SET(MT_EFUSE_CTRL_MODE, mode) | in mt7601u_efuse_read()
153 MT76_SET(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff)); in mt7601u_set_macaddr()
Dmt7601u.h302 mt76_rmw(_dev, _reg, _field, MT76_SET(_field, _val))