Searched refs:MMU (Results 1 - 200 of 529) sorted by relevance

123

/linux-4.4.14/arch/cris/include/asm/
H A Dmmu.h2 * CRIS MMU constants and PTE layout
/linux-4.4.14/arch/alpha/include/asm/
H A Dmmu.h4 /* The alpha MMU context is one "unsigned long" bitmap per CPU */
/linux-4.4.14/include/asm-generic/
H A Dmmu.h6 * Architectures with an MMU need something more complex.
H A Dtlbflush.h6 * If you have an MMU, you need to write your own functions.
/linux-4.4.14/arch/m68k/include/asm/
H A Dmcfmmu.h2 * mcfmmu.h -- definitions for the ColdFire v4e MMU
15 * The MMU support registers are mapped into the address space using
22 * The support registers of the MMU. Names are the sames as those
33 * MMU Control register bit flags
39 * MMU Operation register.
55 * MMU Status register.
63 * MMU Read/Write Tag register.
73 * MMU Read/Write Data register.
94 * Simple access functions for the MMU registers. Nothing fancy
H A Dsun3mmu.h2 * Definitions for Sun3 custom MMU.
11 /* MMU characteristics. */
84 /* Read segmap from hardware MMU. */ sun3_get_segmap()
99 /* Write segmap to hardware MMU. */ sun3_put_segmap()
112 /* Read PTE from hardware MMU. */ sun3_get_pte()
126 /* Write PTE to hardware MMU. */ sun3_put_pte()
H A Dm54xxacr.h93 * If running with the MMU enabled then we need to map the internal
113 * For the non-MMU enabled case we map all of RAM as cacheable.
H A Dpgtable_mm.h127 * The m68k doesn't have any external MMU info: the kernel page
140 /* MMU-specific headers */
/linux-4.4.14/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h24 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
25 #define HP_330 1 /* 16MHz 68020+68851 MMU */
28 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
H A Dbootinfo.h87 * CPU, FPU and MMU types (BI_CPUTYPE, BI_FPUTYPE, BI_MMUTYPE)
124 #define MMUB_68030 1 /* Internal MMU */
125 #define MMUB_68040 2 /* Internal MMU */
126 #define MMUB_68060 3 /* Internal MMU */
129 #define MMUB_COLDFIRE 6 /* Internal MMU */
/linux-4.4.14/arch/m32r/include/asm/
H A Dm32r.h74 * MMU Register
83 #define MATM MMU_REG_BASE /* MMU Address Translation Mode
85 #define MPSZ (0x04 + MMU_REG_BASE) /* MMU Page Size Designation Register */
86 #define MASID (0x08 + MMU_REG_BASE) /* MMU Address Space ID Register */
87 #define MESTS (0x0c + MMU_REG_BASE) /* MMU Exception Status Register */
88 #define MDEVA (0x10 + MMU_REG_BASE) /* MMU Operand Exception Virtual
90 #define MDEVP (0x14 + MMU_REG_BASE) /* MMU Operand Exception Virtual Page
92 #define MPTB (0x18 + MMU_REG_BASE) /* MMU Page Table Base Register */
93 #define MSVA (0x20 + MMU_REG_BASE) /* MMU Search Virtual Address
95 #define MTOP (0x24 + MMU_REG_BASE) /* MMU TLB Operation Register */
96 #define MIDXI (0x28 + MMU_REG_BASE) /* MMU Index Register for
98 #define MIDXD (0x2c + MMU_REG_BASE) /* MMU Index Register for Operand */
H A Dmmu_context.h21 * Cache of MMU context last used.
56 * Get MMU context if needed.
/linux-4.4.14/arch/sparc/include/asm/
H A Dlsu.h14 #define LSU_CONTROL_DM _AC(0x0000000000000008,UL) /* Data MMU enable. */
15 #define LSU_CONTROL_IM _AC(0x0000000000000004,UL) /* Instruction MMU enable. */
H A Dross.h17 /* The MMU control register fields on the HyperSparc.
30 * BM: Boot-Mode. One indicates the MMU is in boot mode.
31 * C: Indicates whether accesses are cachable while the MMU is
40 * ME: MMU Enable -- 0 = MMU is off, 1 = MMU is on
H A Dtsunami.h12 /* The MMU control register on the Tsunami:
31 * ME: MMU Enable, same as all other SRMMUs
H A Dpci_32.h36 * MMU to the PCI Host PCI I/O space window which are translated to the low
H A Dswift.h2 * MMU module.
27 #define SWIFT_EN 0x00000001 /* MMU enable */
H A Dpage_32.h2 * page.h: Various defines and such for MMU operations on the Sparc for
H A Dturbosparc.h31 * ME: MMU enable -- 0 = mmu not translating, 1 = mmu translating
/linux-4.4.14/arch/sh/include/cpu-common/cpu/
H A Dmmu_context.h13 /* No MMU */
/linux-4.4.14/arch/mn10300/include/asm/
H A Dmmu.h12 * MMU context
H A Dmmu_context.h1 /* MN10300 MMU context management
60 * allocate_mmu_context - Allocate storage for the arch-specific MMU data
83 * get an MMU context if one is needed
H A Dcpu-regs.h201 /* MMU control registers */
202 #define MMUCTR __SYSREG(0xc0000090, u32) /* MMU control register */
289 #define MMUFCR __SYSREGC(0xc000009c, u32) /* MMU exception cause */
290 #define MMUFCR_IFC __SYSREGC(0xc000009c, u16) /* MMU instruction excep cause */
291 #define MMUFCR_DFC __SYSREGC(0xc000009e, u16) /* MMU data exception cause */
H A Dpage.h101 * - these mappings are fixed in the MMU
/linux-4.4.14/arch/ia64/hp/common/
H A Dhwsw_iommu.c5 * This is a pseudo I/O MMU which dispatches to the hardware I/O MMU
6 * whenever possible. We assume that the hardware I/O MMU requires
8 * systems (there, the I/O MMU window is mapped at 3-4GB). If a
H A Dsba_iommu.c2 ** IA64 System Bus Adapter (SBA) I/O MMU manager
8 ** Portions (c) 2000 Grant Grundler (from parisc I/O MMU code)
9 ** Portions (c) 1999 Dave S. Miller (from sparc64 I/O MMU code)
63 ** advertising an iommu, but then bypassing it. Since I/O MMU bypassing
203 void __iomem *ioc_hpa; /* I/O MMU base address */
268 ** rather than the HW. I/O MMU allocation algorithms can be
291 * Print the size/location of the IO MMU PDIR.
310 * @ioc: IO MMU structure which owns the pdir we are interested in.
314 * Print one entry of the IO MMU PDIR in human readable form.
342 * @ioc: IO MMU structure which owns the pdir we are interested in.
388 * @ioc: IO MMU structure which owns the pdir we are interested in.
474 * @ioc: IO MMU structure which owns the pdir we are interested in.
624 * @ioc: IO MMU structure which owns the pdir we are interested in.
681 printk(KERN_WARNING "%s: I/O MMU @ %p is" sba_alloc_range()
688 printk(KERN_WARNING "%s: I/O MMU @ %p is" sba_alloc_range()
722 * @ioc: IO MMU structure which owns the pdir we are interested in.
832 * @ioc: IO MMU structure which owns the pdir we are interested in.
1215 * @ioc: IO MMU structure which owns the pdir we are interested in.
1307 * @ioc: IO MMU structure which owns the pdir we are interested in.
/linux-4.4.14/arch/powerpc/boot/
H A Dgamecube-head.S20 * - if the MMU is enabled or not
22 * We enable the caches if not already enabled, enable the MMU with an
31 /* turn the MMU off */
43 /* MMU disabled */
98 /* turn the MMU on */
H A Dwii-head.S20 * - if the MMU is enabled or not
24 * enable the MMU with an identity mapping scheme and jump to the start code.
32 /* turn the MMU off */
44 /* MMU disabled */
122 /* turn the MMU on */
/linux-4.4.14/arch/frv/mm/
H A Dmmu-context.c1 /* mmu-context.c: MMU context allocation and management
41 * make sure a kernel MMU context has a CPU context number
87 * restore the current TLB miss handler mapped page tables into the MMU context and set up a
96 /* save the state of the outgoing MMU context */ change_mm_context()
104 /* select an MMU context number */ change_mm_context()
112 /* restore the state of the incoming MMU context */ change_mm_context()
128 * finished with an MMU context number
151 * display the MMU context currently a process is currently using
166 * (un)pin a process's mm_struct's MMU context ID
H A Dcache-page.c1 /* cache-page.c: whole-page cache wrangling functions for MMU linux
/linux-4.4.14/arch/xtensa/include/asm/
H A Dvectors.h4 * Xtensa macros for MMU V3 Support. Deals with re-mapping the Virtual
5 * Memory Addresses from "Virtual == Physical" to their prevvious V2 MMU
57 /* MMU v3 - XCHAL_HAVE_PTP_MMU == 1 */
60 /* MMU V2 - XCHAL_HAVE_PTP_MMU == 0 */
68 /* MMU Not being used - Virtual == Physical */
108 * are not valid to use with V3 MMU. Non-XCHAL
H A Dinitialize_mmu.h4 * Initializes MMU:
6 * For the new V3 MMU we remap the TLB from virtual == physical
7 * to the standard Linux mapping used in earlier MMU's.
9 * The the MMU we also support a new configuration register that
67 * Have MMU v3
71 # error "MMU v3 requires reloc vectors"
119 /* Step 4: Setup MMU with the old V2 mappings. */
147 /* Jump to self, using MMU v2 mappings. */
H A Dmmu_context.h2 * Switch an MMU context.
30 # error "Linux must have an MMU!"
/linux-4.4.14/arch/arm/boot/compressed/
H A Dhead-xscale.S29 @ disabling MMU and caches
31 bic r0, r0, #0x05 @ clear DC, MMU
H A Dhead-sa1100.S43 @ disabling MMU and caches
45 bic r0, r0, #0x0d @ clear WB, DC, MMU
/linux-4.4.14/arch/powerpc/include/asm/
H A Dpte-fsl-booke.h5 /* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
8 MMU Assist Register 3:
H A Dmmu.h11 * MMU features bit definitions
15 * First half is MMU families
91 /* MMU feature bit sets for various CPUs */
124 /* MMU initialization */
184 /* 64-bit classic hash table MMU */
187 /* 32-bit classic hash table MMU */
196 /* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
H A Dreg_a2.h22 #define SPRN_MMUCR0 0x3fc /* MMU Control Register 0 */
23 #define SPRN_MMUCR1 0x3fd /* MMU Control Register 1 */
24 #define SPRN_MMUCR2 0x3fe /* MMU Control Register 2 */
25 #define SPRN_MMUCR3 0x3ff /* MMU Control Register 3 */
H A Dtlbflush.h62 * TLB flushing for "classic" hash-MMU 32-bit CPUs, 6xx, 7xx, 7xxx
85 * TLB flushing for 64-bit hash-MMU CPUs
173 #error Unsupported MMU type
H A Dpte-hash32.h6 * The "classic" 32-bit implementation of the PowerPC MMU uses a hash
H A Dreg_booke.h78 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
81 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
82 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
88 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
89 #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
148 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
149 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
150 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
151 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
152 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
153 #define SPRN_MAS5 0x153 /* MMU Assist Register 5 */
154 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
164 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
165 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */
178 #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
179 #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
H A Dfeature-fixups.h87 /* MMU feature dependent sections */
101 /* MMU feature sections with alternatives, use BEGIN_FTR_SECTION to start */
H A Dmmu-hash32.h4 * 32-bit hash table MMU support
H A Dmmu-8xx.h17 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
84 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
85 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
H A Dpgtable.h113 * Setting the PTE depends on the MMU type and other factors. It's
121 /* First case is 32-bit Hash MMU in SMP mode with 32-bit PTEs. We use the __set_pte_at()
248 * On machines which use an MMU hash table, we use this to put a
/linux-4.4.14/arch/sparc/include/uapi/asm/
H A Dasi.h42 #define ASI_M_FLUSH_PROBE 0x03 /* Reference MMU Flush/Probe; rw, ss */
43 #define ASI_M_MMUREGS 0x04 /* MMU Registers; rw, ss */
44 #define ASI_M_TLBDIAG 0x05 /* MMU TLB only Diagnostics */
45 #define ASI_M_DIAGS 0x06 /* Reference MMU Diagnostics */
46 #define ASI_M_IODIAG 0x07 /* MMU I/O TLB only Diagnostics */
86 #define ASI_M_BYPASS 0x20 /* Reference MMU bypass; rw, as */
156 #define ASI_MMU 0x21 /* (4V) MMU Context Registers */
202 #define ASI_IMMU 0x50 /* Insn-MMU main register space */
203 #define ASI_IMMU_TSB_8KB_PTR 0x51 /* Insn-MMU 8KB TSB pointer reg */
204 #define ASI_IMMU_TSB_64KB_PTR 0x52 /* Insn-MMU 64KB TSB pointer reg */
205 #define ASI_ITLB_DATA_IN 0x54 /* Insn-MMU TLB data in reg */
206 #define ASI_ITLB_DATA_ACCESS 0x55 /* Insn-MMU TLB data access reg */
207 #define ASI_ITLB_TAG_READ 0x56 /* Insn-MMU TLB tag read reg */
208 #define ASI_IMMU_DEMAP 0x57 /* Insn-MMU TLB demap */
209 #define ASI_DMMU 0x58 /* Data-MMU main register space */
210 #define ASI_DMMU_TSB_8KB_PTR 0x59 /* Data-MMU 8KB TSB pointer reg */
211 #define ASI_DMMU_TSB_64KB_PTR 0x5a /* Data-MMU 16KB TSB pointer reg */
212 #define ASI_DMMU_TSB_DIRECT_PTR 0x5b /* Data-MMU TSB direct pointer reg */
213 #define ASI_DTLB_DATA_IN 0x5c /* Data-MMU TLB data in reg */
214 #define ASI_DTLB_DATA_ACCESS 0x5d /* Data-MMU TLB data access reg */
215 #define ASI_DTLB_TAG_READ 0x5e /* Data-MMU TLB tag read reg */
216 #define ASI_DMMU_DEMAP 0x5f /* Data-MMU TLB demap */
H A Dpstate.h14 #define PSTATE_MG _AC(0x0000000000000400,UL) /* MMU Globals. */
51 #define TSTATE_MG _AC(0x0000000000040000,UL) /* MMU Globals. */
H A Dtraps.h68 #define SP_TRAP_DMM 0x2c /* Data Access MMU Miss ??? */
69 #define SP_TRAP_IMM 0x3c /* Instruction Access MMU Miss ??? */
/linux-4.4.14/arch/m68k/kernel/
H A Drelocate_kernel.S8 #define MMU_BASE 8 /* MMU flags base in cpu_mmu_flags */
18 /* Disable MMU */
33 pmove %tc,%d0 /* Disable MMU */
67 movec %d0,%tc /* Disable MMU */
/linux-4.4.14/arch/microblaze/include/asm/
H A Dkgdb.h14 * 7 32-bit MMU Regs (redr, rpid, rzpr, rtlbx, rtlbsx, rtlblo, rtlbhi)
H A Dprocessor.h42 * TASK_SIZE on MMU cpu is usually 1GB. However, on no-MMU arch, both
88 * This is used to define STACK_TOP, and with MMU it must be below
89 * kernel base to select the correct PGD when handling MMU exceptions.
H A Dpage.h7 * Changes for MMU support:
53 * using MMU this corresponds to the first free page in physical memory (aligned
62 * PAGE_OFFSET -- the first address of the first page of memory. With MMU
180 /* Convert between virtual and physical address for MMU. */
H A Dmmu_context_mm.h24 * to spread out the entries in the MMU hash table.
45 * Set the current MMU context.
H A Dpgtable.h22 #define pgd_present(pgd) (1) /* pages are always present on non MMU */
29 #define PAGE_NONE __pgprot(0) /* these mean nothing to non MMU */
30 #define PAGE_SHARED __pgprot(0) /* these mean nothing to non MMU */
31 #define PAGE_COPY __pgprot(0) /* these mean nothing to non MMU */
32 #define PAGE_READONLY __pgprot(0) /* these mean nothing to non MMU */
33 #define PAGE_KERNEL __pgprot(0) /* these mean nothing to non MMU */
113 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash pte_mkspecial()
/linux-4.4.14/arch/microblaze/kernel/
H A DMakefile32 obj-y += entry$(MMU).o
H A Dmisc.S2 * Miscellaneous low-level MMU functions.
24 * Flush MMU TLB
48 * Flush MMU TLB for a particular address (in r5)
H A Dvmlinux.lds.S62 . = ALIGN(PAGE_SIZE); /* page aligned when MMU used */
129 /* page aligned when MMU used */
H A Dhead.S6 * MMU code derived from arch/ppc/kernel/head_4xx.S:
12 * Low-level exception handers, MMU support, and rewrite.
148 /* We have to turn on the MMU right away. */
151 * Set up the initial MMU state so we can do the first level of
328 rted r15,0 /* enables MMU */
359 * Initialize the MMU.
389 rted r17, 0 /* enable MMU and jump to start_kernel */
H A Dhw_exception_handler.S11 * MMU code derived from arch/ppc/kernel/head_4xx.S:
17 * Low-level exception handers, MMU support, and rewrite.
56 * - Privileged instruction exception (MMU)
57 * - Data storage exception (MMU)
58 * - Instruction storage exception (MMU)
59 * - Data TLB miss exception (MMU)
60 * - Instruction TLB miss exception (MMU)
237 * MMU kernel uses the same 'pt_pool_space' pointed space
243 * MMU exception handler has different handling compare to no MMU kernel.
244 * Exception handler use jump table for directing of what happen. For MMU kernel
245 * is this approach better because MMU relate exception are handled by asm code
246 * in this file. In compare to with MMU expect of unaligned exception
460 * This handler perform the access, and returns, except for MMU when
704 * As the name implies, translation is not in the MMU, so search the
936 /* Unaligned data access exception last on a 4k page for MMU.
/linux-4.4.14/arch/m68k/hp300/
H A Dreboot.S7 * good stuff that head.S did when we started up. The caches and MMU must be
/linux-4.4.14/arch/arc/include/asm/
H A Dmmu.h22 /* MMU Management regs */
42 /* Bits in MMU PID register */
75 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
H A Dtlb-mmu1.h23 ; Calculate set index for 2-way MMU
24 ; -avoiding use of GetIndex from MMU
48 ; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
55 and.f r0,r0,0x000fe000 /* 2-way MMU mask */
94 lr r1,[ARC_REG_TLBINDEX] /* r1 = index where MMU wants to put data */
H A Dmmu_context.h28 * ARC MMU provides 8-bit ASID (0..255) to TAG TLB entries, allowing entries
39 * The 32 bit @asid_cpu (and mm->asid) have 8 bits MMU PID and rest 24 bits
44 #define MM_CTXT_ASID_MASK 0x000000ff /* MMU PID reg :8 bit PID */
58 * Also set the MMU PID register to existing/updated ASID
128 /* Prepare the MMU for task: setup PID reg with allocated ASID
150 /* PGD cached in MMU reg to avoid 3 mem lookups: task->mm->pgd */ switch_mm()
H A Dpgtable.h9 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
15 * vineetg: Mar 2011 - changes to accomodate MMU TLB Page Descriptor mods
18 * -Per my request, MMU V3 changes the layout of some of the bits
46 * ARC700 MMU only deals with softare managed TLB entries.
50 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible becoz they live in
53 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos
69 #else /* MMU v3 onwards */
201 /* Optimal Sizing of Pg Tbl - based on MMU page size */
343 * in a MMU register
/linux-4.4.14/arch/metag/include/asm/
H A Dmmu.h13 /* Software pgd base pointer used for Meta 1.x MMU. */
37 /* Get the virtual base address of the MMU */
40 /* Initialize the MMU. */
H A Dmmu_context.h61 * The permission bits apply to MMU table region which gives a 2MB load_pgd()
67 /* Set new MMU base address */ load_pgd()
H A Dpgtable-bits.h11 * Definitions for MMU descriptors
/linux-4.4.14/arch/powerpc/mm/
H A Dinit_32.c124 * and sets up the page tables and the MMU hardware ready to go.
129 ppc_md.progress("MMU:enter", 0x111); MMU_init()
168 /* Initialize the MMU hardware */ MMU_init()
170 ppc_md.progress("MMU:hw init", 0x300); MMU_init()
175 ppc_md.progress("MMU:mapin", 0x301); MMU_init()
183 ppc_md.progress("MMU:setio", 0x302); MMU_init()
186 ppc_md.progress("MMU:exit", 0x211); MMU_init()
H A Dmmu_context_hash32.c2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU substantially follows the
52 * to spread out the entries in the MMU hash table. Note, if this
H A Dmmu_context_nohash.c2 * This file contains the routines for handling the MMU on those
3 * PowerPC implementations where the MMU is not using the hash
209 pr_err("MMU: Context %d is %s and MM is %p !\n", context_check_map()
215 pr_err("MMU: Free context count out of sync ! (%d vs %d)\n", context_check_map()
220 pr_err("MMU: More active contexts than CPUs ! (%d vs %d)\n", context_check_map()
223 pr_err("MMU: Context 0 has been freed !!!\n"); context_check_map()
257 pr_err("MMU: mm 0x%p has id %d but context_mm[%d] says 0x%p\n", switch_mmu_context()
320 /* Flick the MMU and release lock */ switch_mmu_context()
387 pr_devel("MMU: Allocating stale context map for CPU %d\n", cpu); mmu_context_cpu_notify()
395 pr_devel("MMU: Freeing stale context map for CPU %d\n", cpu); mmu_context_cpu_notify()
476 "MMU: Allocated %zu bytes of context maps for %d contexts\n", mmu_context_init()
H A D40x_mmu.c2 * This file contains the routines for initializing the MMU
56 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
H A D44x_mmu.c5 * This file contains the routines for initializing the MMU
65 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
135 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
H A Dtlb_nohash.c3 * On machines where the MMU does not use a hash table to store virtual to
52 * This struct lists the sw-supported page sizes. The hardawre MMU may support
547 pr_info("MMU: Supported page sizes\n"); setup_page_sizes()
585 pr_info("MMU: Book3E HW tablewalk %s\n", setup_mmu_htw()
590 * Early initialization of the MMU TLB code
656 * the MMU configuration early_init_this_mmu()
H A Dhugetlbpage-book3e.c2 * PPC Huge TLB Page Support for Book3E MMU
H A Dmmu_context_hash64.c2 * MMU context allocation for 64-bit kernels.
/linux-4.4.14/arch/arc/mm/
H A Dtlb.c21 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
24 * vineetg: April 2011 : Preparing for MMU V3
25 * -MMU v2/v3 BCRs decoded differently
30 * = walks MMU only if range spans < 32 entries, as opposed to 256
33 * -Changes related to MMU v2 (Rel 4.8)
36 * -In TLB Flush operations (Metal Fix MMU) there is a explict command to
61 /* Need for ARC MMU v2
63 * ARC700 MMU-v1 had a Joint-TLB for Code and Data and is 2 way set-assoc.
152 * ARC700 MMU caches recently used J-TLB entries (RAM) as uTLBs (FLOPs)
154 * New IVUTLB cmd in MMU v2 explictly invalidates the uTLB
157 * -For v2 MMU calls Flush uTLB Cmd
158 * -For v1 MMU does nothing (except for Metal Fix v1 MMU)
167 /* MMU v2 introduced the uTLB Flush command. utlb_invalidate()
170 * return lkup err - because the entry didnt exist in MMU. utlb_invalidate()
172 * flush. This was fixed in MMU v3 hence not needed any more utlb_invalidate()
200 * If Not already present get a free slot from MMU. tlb_entry_insert()
212 * Commit the Entry to MMU tlb_entry_insert()
246 * Un-conditionally (without lookup) erase the entire MMU contents
297 * Only for fork( ) do we need to move parent to a new MMU ctxt, local_flush_tlb_mm()
362 /* Flush the kernel TLB entries - vmalloc/modules (Global from MMU perspective)
393 * Delete TLB entry in MMU for a given page (??? address)
523 * -it ASID for TLB entry is fetched from MMU ASID reg (valid for curr) create_tlb()
527 * -Using vma->mm->context{ASID,SASID}, as opposed to MMU reg. create_tlb()
566 * ARC MMU provides fully orthogonal access bits for K/U mode, create_tlb()
568 * Here we convert 3 PTE bits into 6 MMU bits: create_tlb()
588 * -pre-install the corresponding TLB entry into MMU
644 * - MMU page size (typical 8K, RTL fixed)
801 "MMU [v%x]\t: %dk PAGE, %sJTLB %d (%dx%d), uDTLB %d, uITLB %d %s%s\n", arc_mmu_mumbojumbo()
817 /* For efficiency sake, kernel is compile time built for a MMU ver arc_mmu_init()
819 * Linux built for MMU V2, if run on MMU V1 will break down because V1 arc_mmu_init()
821 * On the other hand, Linux built for V1 if run on MMU V2 will do arc_mmu_init()
823 * Similarly MMU V3 has new features which won't work on older MMU arc_mmu_init()
826 panic("MMU ver %d doesn't match kernel built for %d...\n", arc_mmu_init()
831 panic("MMU pg size != PAGE_SIZE (%luk)\n", TO_KB(PAGE_SIZE)); arc_mmu_init()
835 panic("MMU Super pg size != Linux HPAGE_PMD_SIZE (%luM)\n", arc_mmu_init()
841 /* Enable the MMU */ arc_mmu_init()
863 * MMU cmd getIndex(vaddr) abstracts that out.
868 /* Handling of Duplicate PD (TLB entry) in MMU.
870 * -MMU complaints not at the time of duplicate PD installation, but at the
888 /* re-enable the MMU */ do_tlb_overlap_fault()
H A Dioremap.c26 /* If the region is h/w uncached, avoid MMU mappings */ ioremap()
37 * However unline vanilla ioremap which bypasses ARC MMU for addresses in
38 * ARC hardware uncached region, this one still goes thru the MMU as caller
H A Dtlbex.S11 * -MMU v1: moved out legacy code into a seperate file
12 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
16 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
101 ; VERIFY if the ASID in MMU-PID Reg is same as
149 ; we use the MMU PID Reg to get current ASID.
165 and r2, r0, 0xFF ; MMU PID bits only for comparison
274 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
281 ; Commit the TLB entry into MMU
397 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
399 ; But only for old MMU or one with Metal Fix
H A Dcache.c177 * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3)
189 * MMU v1/v2 (Fixed Page Size 8k)
207 * MMU v3
209 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
297 * This is technically for MMU v4, using the MMU v3 programming model __cache_line_loop_v3()
318 * In HS38x (MMU v4), I-cache is VIPT (can alias), D-cache is PIPT
324 * respectively, similar to MMU v3 programming model, hence
928 panic("Cache ver [%d] doesn't match MMU ver [%d]\n", arc_cache_init()
932 * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG arc_cache_init()
933 * pair to provide vaddr/paddr respectively, just as in MMU v3 arc_cache_init()
/linux-4.4.14/arch/metag/mm/
H A Dmmu-meta1.c4 * Meta 1 MMU handling code.
125 /* Find the base of our MMU pgd table */ mmu_get_base()
138 * Now copy over any MMU pgd entries already in the mmu page tables mmu_init()
149 /* copy over the current MMU value */ mmu_init()
H A Dmmu-meta2.c4 * Meta 2 enhanced mode MMU handling code.
100 pr_warn("Fixing priv protection on T%d %s MMU table region\n", repriv_mmu_tables()
120 * If a full suspend to RAM has happened then the original bad MMU table mmu_resume()
145 * Now copy over any MMU pgd entries already in the mmu page tables mmu_init()
156 /* copy over the current MMU value */ mmu_init()
/linux-4.4.14/arch/unicore32/kernel/
H A Dhead.S55 * are: MMU = off, D-cache = off, I-cache = dont care
95 * cater for the MMU enable. This identity mapping
129 * Initialise TLB, Caches, and MMU state ready to switch the MMU
145 * Setup common bits before finally enabling the MMU. Essentially
167 * Enable the MMU. This completely changes the structure of the visible
206 * The following fragment of code is executed with the MMU on in MMU mode,
H A Ddebug-macro.S49 tst \rx, #1 @ MMU enabled?
/linux-4.4.14/arch/mn10300/mm/
H A Dmmu-context.c1 /* MN10300 MMU context allocation and management
18 * list of the MMU contexts last allocated on each CPU
H A Dinit.c55 * the MMU */ paging_init()
/linux-4.4.14/arch/frv/include/asm/
H A Dmmu.h1 /* mmu.h: memory management context for FR-V with or without MMU support
17 unsigned short id; /* MMU context ID */
H A Dsegment.h1 /* segment.h: MMU segment settings
H A Dmmu_context.h1 /* mmu_context.h: MMU context management routines
H A Dgdb-stub.h126 * - gr31 is destroyed on entry to the gdbstub if !MMU
127 * - gr31 is saved in scr3 on entry to the gdbstub if in !MMU
H A Dspr-regs.h148 #define HSR0_EXMMU 0x01000000 /* enable extended MMU mode */
149 #define HSR0_EDMMU 0x02000000 /* enable data MMU */
150 #define HSR0_EIMMU 0x04000000 /* enable instruction MMU */
233 #define ESR0_ATXC_MMU_MISS 0x00000000 /* - MMU miss exception and more (?) */
236 #define ESR0_ATXC_AMRTLB_MISS 0x00a00000 /* - MMU/TLB miss exception */
/linux-4.4.14/arch/cris/arch-v32/mm/
H A Dinit.c2 * Set up paging and the MMU.
103 /* Update the instruction MMU. */ cris_mmu_init()
110 /* Update the data MMU. */ cris_mmu_init()
120 * The MMU has been enabled ever since head.S but just to make it cris_mmu_init()
132 printk("Setting up paging and the MMU.\n"); paging_init()
H A Dtlb.c60 SUPP_BANK_SEL(mmu); /* Select the MMU */ __flush_tlb_all()
185 /* Make sure there is a MMU context. */ switch_mm()
198 /* Switch context in the MMU. */ switch_mm()
H A Dmmu.S44 move \mmu, $srs ; Select MMU support register bank
95 move \mmu, $srs ; Select MMU support register bank
201 ; This is the MMU bus fault handlers.
/linux-4.4.14/arch/sh/include/asm/
H A Dmmu_context.h18 * The MMU "context" consists of two things:
55 * Get MMU context if needed.
152 * If this processor has an MMU, we need methods to turn it off/on ..
160 /* Enable MMU */ enable_mmu()
182 * MMU control handlers for processors lacking memory
H A Dsuspend.h42 /* MMU */ sh_mobile_setup_cpuidle()
93 #define SUSP_SH_MMU (1 << 5) /* Save/restore MMU and cache */
/linux-4.4.14/arch/arm/mach-mvebu/
H A Dcoherency_ll.S33 tst r1, #CR_M @ Check MMU bit enabled
37 * MMU is disabled, use the physical address of the coherency
51 * MMU is enabled, use the virtual address of the coherency
80 * MMU can be disabled. The Armada XP SoC has an exclusive monitor
82 * that, exclusive transactions are functional even when the MMU is
H A Dpmsu_ll.S34 * Disable the MMU that might have been enabled in BootROM if
/linux-4.4.14/arch/avr32/include/asm/
H A Dmmu_context.h20 * The MMU "context" consists of two things:
34 /* Cache of MMU context last used */
38 * Get MMU context if needed
/linux-4.4.14/arch/arm/include/asm/
H A Dcp15.h9 #define CR_M (1 << 0) /* MMU enable */
17 #define CR_S (1 << 8) /* System MMU protection */
18 #define CR_R (1 << 9) /* ROM MMU protection */
/linux-4.4.14/arch/unicore32/include/asm/
H A Dhwdef-copro.h16 #define CR_M (1 << 0) /* MMU enable */
/linux-4.4.14/arch/x86/include/asm/
H A Dagp.h8 * Functions to keep the agpgart mappings coherent with the MMU. The
/linux-4.4.14/fs/ramfs/
H A Dfile-mmu.c1 /* file-mmu.c: ramfs MMU-based file operations
/linux-4.4.14/arch/powerpc/platforms/512x/
H A Dmpc512x_generic.c37 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc5121_ads.c56 * Called very early, MMU is off, device-tree isn't unflattened
/linux-4.4.14/arch/powerpc/platforms/83xx/
H A Dasp834x.c42 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc831x_rdb.c45 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc836x_rdk.c44 * Called very early, MMU is off, device-tree isn't unflattened.
H A Dmpc830x_rdb.c45 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc834x_itx.c69 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc837x_rdb.c72 * Called very early, MMU is off, device-tree isn't unflattened
H A Dsbc834x.c59 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc832x_mds.c103 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc834x_mds.c90 * Called very early, MMU is off, device-tree isn't unflattened
H A Dmpc837x_mds.c92 * Called very early, MMU is off, device-tree isn't unflattened
/linux-4.4.14/arch/sh/include/cpu-sh3/cpu/
H A Dmmu_context.h18 #define MMUCR 0xFFFFFFE0 /* MMU Control Register */
/linux-4.4.14/arch/sparc/kernel/
H A Divec.S4 * [high 32-bits] MMU Context Argument 0, place in %g5
H A Dhvtramp.S25 * MMU entries we need to load up.
27 * After we set things up we enable the MMU and call
H A Dleon_pmc.c47 * MMU does not get a TLB miss here by using the MMU BYPASS ASI. pmc_leon_idle_fixup()
H A Detrap_32.S216 /* Call MMU-architecture dependent stack checking
237 LEON_PI( lda [%g0] ASI_LEON_MMUREGS, %glob_tmp) ! read MMU control
238 SUN_PI_( lda [%g0] ASI_M_MMUREGS, %glob_tmp) ! read MMU control
H A Dsun4v_tlb_miss.S47 /* Load MMU Miss base into %g2. */
93 /* Load MMU Miss base into %g2. */
138 /* Load MMU Miss base into %g5. */
/linux-4.4.14/arch/m32r/boot/compressed/
H A Dm32r_sio.c28 * fpga configuration program uses MMU, and define map as same as
H A Dhead.S125 srli r0, 31 /* MMU is ON or OFF */
155 srli r0, 31 /* MMU is ON or OFF */
/linux-4.4.14/arch/arm/mach-ks8695/include/mach/
H A Dhardware.h33 * head debug code as the initial MMU setup only deals in L1 sections.
/linux-4.4.14/arch/arm/mm/
H A Dpv-fixup-asm.S26 bic ip, r8, #CR_M @ disable caches and MMU
83 mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
H A Dproc-sa110.S11 * MMU functions for SA110
113 * Clean the specified entry of any caches such that the MMU
H A Dproc-v6.S62 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
186 * Initialise TLB, Caches, and MMU state ready to switch the MMU
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dsleep.S37 * entered with no caches live and the MMU disabled. It will then
38 * restore the MMU and other basic CP registers saved and restart
/linux-4.4.14/arch/arm/kernel/
H A Dsuspend.c28 * the MMU-enable code, required for resuming. On successful cpu_suspend()
75 * are to be retrieved with the MMU off that __cpu_suspend_save()
H A Dhead-common.S72 * The following fragment of code is executed with the MMU on in MMU mode,
142 * for the __proc_info lists since we aren't running with the MMU on
/linux-4.4.14/arch/powerpc/kvm/
H A Dbook3s_64_mmu.c157 dprintk("MMU: page=0x%x sdr1=0x%llx pteg=0x%llx vsid=0x%llx\n", kvmppc_mmu_book3s_64_get_pteg()
337 dprintk("KVM MMU: Translated 0x%lx [0x%llx] -> 0x%llx " kvmppc_mmu_book3s_64_xlate()
374 dprintk("KVM MMU: Trigger segment fault\n"); kvmppc_mmu_book3s_64_xlate()
385 dprintk("KVM MMU: slbmte(0x%llx, 0x%llx)\n", rs, rb); kvmppc_mmu_book3s_64_slbmte()
459 dprintk("KVM MMU: slbie(0x%llx)\n", ea); kvmppc_mmu_book3s_64_slbie()
466 dprintk("KVM MMU: slbie(0x%llx, 0x%llx)\n", ea, slbe->esid); kvmppc_mmu_book3s_64_slbie()
480 dprintk("KVM MMU: slbia()\n"); kvmppc_mmu_book3s_64_slbia()
517 dprintk("KVM MMU: mtsrin(0x%x, 0x%lx)\n", srnum, value); kvmppc_mmu_book3s_64_mtsrin()
541 dprintk("KVM MMU: tlbie(0x%lx)\n", va); kvmppc_mmu_book3s_64_tlbie()
623 * 64k pages, the host MMU supports 64k pages and kvmppc_mmu_book3s_64_esid_to_vsid()
H A Dbook3s_32_mmu.c128 dprintk("MMU: pc=0x%lx eaddr=0x%lx sdr1=0x%llx pteg=0x%x vsid=0x%x\n", kvmppc_mmu_book3s_32_get_pteg()
260 dprintk_pte("MMU: Found PTE -> %x %x - %x\n", kvmppc_mmu_book3s_32_xlate_pte()
293 dprintk_pte("KVM MMU: No PTE found (sdr1=0x%llx ptegp=0x%lx)\n", kvmppc_mmu_book3s_32_xlate_pte()
/linux-4.4.14/arch/sh/kernel/
H A Dhead_64.S22 * MMU defines: TLB boundaries.
39 * MMU defines: Fixed TLBs.
124 * . SR.MMU = 0 (MMU Disabled)
129 * . prevent speculative fetch onto device memory while MMU is off
137 * . enable MMU and caches
253 * Enable Caches and MMU. Do the first non-PIC jump.
H A Dreboot.c29 /* Destroy all of the TLBs in preparation for reset by MMU */ native_machine_restart()
/linux-4.4.14/arch/arm64/kernel/
H A Dhead.S59 * MMU = off, D-cache = off, I-cache = on or off,
66 * that are useful before the MMU is enabled. The allocations are described
219 * On return, the CPU will be ready for the MMU to be turned on and
223 // MMU has been enabled
239 // MMU off
307 * - identity mapping to enable the MMU (low address, TTBR0)
308 * - first few MB of the kernel linear mapping to jump to once the MMU has
400 * accesses (MMU disabled), invalidate the idmap and swapper page
414 * The following fragment of code is executed with the MMU enabled.
607 ldr x27, =__secondary_switched // address to jump to after enabling the MMU
619 * Enable the MMU.
621 * x0 = SCTLR_EL1 value for turning on the MMU.
H A Defi-entry.S25 * * MMU on with identity-mapped RAM
94 /* Turn off Dcache and MMU */
H A Dsuspend.c30 * Only flush the context that must be retrieved with the MMU __cpu_suspend_save()
91 * idmap to enable the MMU; set the TTBR0 to the reserved cpu_suspend()
/linux-4.4.14/arch/arm/kvm/
H A Dinit.S37 * - Enable the MMU with the boot pgd
49 * Provides the basic HYP init, and enable the MMU.
114 @ - MMU: enabled (this code must be run from an identity mapping)
/linux-4.4.14/sound/pci/aw2/
H A Daw2-saa7146.c164 pages. So we don't need to use MMU of saa7146. snd_aw2_saa7146_pcm_init_playback()
167 /* No MMU -> nothing to do with PageA1, we only configure the limit of snd_aw2_saa7146_pcm_init_playback()
169 /* Disable MMU */ snd_aw2_saa7146_pcm_init_playback()
221 pages. So we don't need to use MMU of saa7146. snd_aw2_saa7146_pcm_init_capture()
224 /* No MMU -> nothing to do with PageA1, we only configure the limit of snd_aw2_saa7146_pcm_init_capture()
226 /* Disable MMU */ snd_aw2_saa7146_pcm_init_capture()
/linux-4.4.14/arch/cris/include/arch-v10/arch/
H A Dmmu.h2 * CRIS MMU constants and PTE layout
8 /* type used in struct mm to couple an MMU context to an active mm */
/linux-4.4.14/arch/sh/mm/
H A Dtlbflush_32.c2 * TLB flushing operations for SH with an MMU.
111 /* Instead of invalidating each TLB, we get new MMU context. */ local_flush_tlb_mm()
H A Dtlbex_32.c2 * TLB miss handler for SH with an MMU.
H A Dtlb-sh3.c87 * Write to the MMU control register's bit: local_flush_tlb_all()
/linux-4.4.14/arch/microblaze/
H A DMakefile66 MMU := -nommu macro
69 export MMU DTB
/linux-4.4.14/arch/nios2/mm/
H A Dmmu_context.c2 * MMU context handling.
41 * Initialize MMU context management stuff.
/linux-4.4.14/arch/cris/mm/
H A Dtlb.c67 * if needed, get a new MMU context for the mm. otherwise nothing is done.
77 /* called by __exit_mm to destroy the used MMU context if any before
/linux-4.4.14/drivers/iommu/
H A Dexynos-iommu.c104 #define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */
105 #define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
106 #define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
241 /* return true if the System MMU was not active previously set_sysmmu_active()
248 /* return true if the System MMU is needed to be disabled */ set_sysmmu_inactive()
348 pr_err("%s: Fault is not occurred by System MMU '%s'!\n", exynos_sysmmu_irq()
680 /* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */ exynos_iommu_domain_alloc()
843 * MMU v3.3. alloc_lv2entry()
891 * Flushing FLPD cache in System MMU v3.3 that may cache a FLPD lv1set_section()
934 * System MMU v3.x has advanced logic to improve address translation
937 * System MMU reports page fault if the cached fault entry is hit even though
944 * at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
947 * the following sizes for System MMU v3.1 and v3.2.
948 * System MMU v3.1: 128KiB
949 * System MMU v3.2: 256KiB
951 * Because System MMU v3.3 caches page table entries more aggressively, it needs
1033 /* workaround for h/w bug in System MMU v3.3 */ exynos_iommu_unmap()
H A Domap-iommu.h77 * MMU Register offsets
100 * MMU Register bit definitions
/linux-4.4.14/drivers/gpu/drm/vc4/
H A Dvc4_bo.c12 * access to system memory with no MMU in between. To support it, we
/linux-4.4.14/arch/powerpc/kernel/
H A Dhead_8xx.S6 * Low-level exception handlers and MMU support
94 * We first initialize the MMU to support 8M byte pages, then load one
105 /* We have to turn on the MMU right away so we get cache modes
122 rfi /* enables MMU */
370 /* The Linux PTE won't go exactly into the MMU TLB.
374 * of the MMU.
444 /* The Linux PTE won't go exactly into the MMU TLB.
448 * of the MMU.
674 bl early_init /* We have to do this with MMU on */
677 * Decide what sort of machine this is and initialize the MMU.
727 /* Now turn on the MMU for real! */
733 rfi /* enable MMU and jump to start_kernel */
735 /* Set up the initial MMU state so we can do the first level of
751 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
860 * Set up to use a given MMU context.
864 * into the MMU base register, and set the ASID compare register with
H A Dcpu_setup_ppc970.S25 /* Make sure HID4:rm_ci is off before MMU is turned off, that large
145 /* Called with no MMU context (typically MSR:IR/DR off) to
H A Dswsusp_32.S150 * disabling the MMU completely isn't a good option for
230 /* Restore the BATs, and SDR1. Then we can turn on the MMU.
309 /* restore the MSR and turn on the MMU */
341 * down the instruction MMU, we could just flip back MSR-DR on.
H A Dhead_64.S8 * Low-level exception handlers and MMU support
53 * 1. The MMU is off & open firmware is running in real mode.
56 * 1. The MMU is off, processor in HV mode, primary CPU enters at 0
62 * 1. The MMU is on running in AS0 in a state defined in ePAPR
336 * Turn the MMU off.
337 * Assumes we're mapped EA == RA if the MMU is on.
398 /* Setup some critical 970 SPRs before switching MMU off */
412 /* Switch off MMU if not already off */
698 /* enable MMU and jump to start_secondary */
755 * the MMU is on we need our TOC to be a virtual address otherwise
757 * accessed later with the MMU on. We use tovirt() at the call
H A Dsetup_64.c130 WARN_ONCE("%s: unsupported MMU configuration -- expect problems\n", for_each_possible_cpu()
227 * with MMU translation disabled. We rely on the "feature" of
293 * (the MMU has been setup), so adjust the MSR in the PACA to early_setup()
314 * Right after we return from this function, we turn on the MMU early_setup()
316 * no longer work, it needs to switch to using a real MMU early_setup()
334 * (the MMU has been setup), so adjust the MSR in the PACA to early_setup_secondary()
731 /* Initialize the MMU context management stuff */ setup_arch()
H A Dhead_40x.S7 * Low-level exception handers, MMU support, and rewrite.
63 /* We have to turn on the MMU right away so we get cache modes
79 rfi /* enables MMU */
447 * As the name implies, translation is not in the MMU, so search the
696 andi. r10,r9,MSR_IR|MSR_PR /* check supervisor + MMU off */
844 bl early_init /* We have to do this with MMU on */
847 * Decide what sort of machine this is and initialize the MMU.
885 /* Now turn on the MMU for real! */
892 rfi /* enable MMU and jump to start_kernel */
895 /* Set up the initial MMU state so we can do the first level of
H A Dhead_32.S8 * Low-level exception handlers and MMU support
152 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
188 * The MMU is off at this point.
201 * Actually no, pmac doesn't have it on any more. BootX enters with MMU
212 RFI /* enables MMU */
859 /* load up the MMU */
870 /* enable MMU and jump to start_secondary */
898 * Load stuff into the MMU. Intended to be called with
964 * and set up the MMU.
1003 /* Now turn on the MMU for real! */
1121 andi. r0,r3,MSR_DR|MSR_IR /* MMU enabled? */
1233 * We first disable the MMU, and then jump to the ROM reset address.
/linux-4.4.14/arch/powerpc/platforms/44x/
H A Debony.c48 * Called very early, MMU is off, device-tree isn't unflattened
/linux-4.4.14/arch/powerpc/platforms/52xx/
H A Dlite5200_sleep.S58 * even when CONFIG_BDI* is disabled and MMU XLAT commented; heisenbug?))
288 /* save MMU regs */
341 /* MMU is not up yet */
362 /* restore MMU regs */
H A Dmpc5200_simple.c69 * Called very early, MMU is off, device-tree isn't unflattened
/linux-4.4.14/arch/score/kernel/
H A Dhead.S54 ori r30, 0x02 /* enable MMU. */
/linux-4.4.14/arch/sh/include/cpu-sh4/cpu/
H A Dmmu_context.h20 #define MMUCR 0xFF000010 /* MMU Control Register */
/linux-4.4.14/arch/microblaze/mm/
H A Dmmu_context.c2 * This file contains the routines for handling the MMU.
H A Dinit.c29 /* Use for MMU and noMMU because of PCI generic code */
298 * MMU_init_hw does the chip-specific initialization of the MMU hardware.
322 * and sets up the page tables and the MMU hardware ready to go.
376 /* Initialize the MMU hardware */ mmu_init()
/linux-4.4.14/arch/cris/include/uapi/arch-v10/arch/
H A Dsvinto.h23 /* Do remember that DMA does not go through the MMU and needs
/linux-4.4.14/arch/m32r/kernel/
H A Dhead.S142 ;; enable MMU
151 jmp r5 ; enable MMU
206 ;; disable MMU
217 jmp r4 ; disable MMU
/linux-4.4.14/arch/arm/mach-uniphier/
H A Dheadsmp.S27 bic r0, r0, #(CR_C | CR_M) @ Disable MMU and Dcache
/linux-4.4.14/arch/arm/include/debug/
H A Dsa1100.S23 tst \rp, #1 @ MMU enabled?
/linux-4.4.14/arch/cris/arch-v32/kernel/
H A Dhead.S55 ;; Setup and enable the MMU. Use same configuration for both the data
56 ;; and the instruction MMU.
59 ;; bank 1 is the instruction MMU, bank 2 is the data MMU.
133 ;; Update instruction MMU.
142 ;; Update data MMU.
151 ;; Enable data and instruction MMU.
H A Dtraps.c49 printk(" Data MMU Cause: %08lx\n", d_mmu_cause); show_registers()
50 printk("Instruction MMU Cause: %08lx\n", i_mmu_cause); show_registers()
/linux-4.4.14/arch/openrisc/include/asm/
H A Dspr_defs.h66 /* Data MMU group */
74 /* Instruction MMU group */
150 #define SPR_UPR_DMP 0x00000008 /* Data MMU present */
151 #define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
210 #define SPR_SR_DME 0x00000020 /* Data MMU Enable */
211 #define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
226 * Bit definitions for the Data MMU Control Register
235 * Bit definitions for the Instruction MMU Control Register
342 * Bit definitions for Data MMU Configuration Register
358 * Bit definitions for Instruction MMU Configuration Register
/linux-4.4.14/arch/unicore32/boot/compressed/
H A Dhead.S149 * Turn off the Cache and MMU.
151 mov r0, #0 @ disable i/d cache and MMU
/linux-4.4.14/arch/sh/boot/compressed/
H A Dhead_64.S110 * Enable the MMU.
142 * Disable the MMU.
/linux-4.4.14/arch/m68k/mm/
H A Dmcfmmu.c5 * Implementations of mm routines specific to the Coldfire MMU.
176 * use an MMU hash table - this is true for 8xx and 4xx.
H A Dsun3mmu.c4 * Implementations of mm routines specific to the sun3 MMU.
/linux-4.4.14/arch/openrisc/mm/
H A Dtlb.c78 * MMU's with a single way and is hard-coded that way.
174 /* called by __exit_mm to destroy the used MMU context if any before
/linux-4.4.14/arch/frv/kernel/
H A Dfutex.c18 * the various futex operations; MMU fault checking is ignored under no-MMU
/linux-4.4.14/arch/m32r/boot/
H A Dsetup.S114 * if with MMU, TLB on.
115 * if with no MMU, only jump.
/linux-4.4.14/arch/arm64/kvm/
H A Dhyp-init.S76 * level for the HYP ID map, or we won't be able to enable the EL2 MMU.
118 /* MMU is now enabled. Get ready for the trampoline dance */
/linux-4.4.14/arch/sparc/power/
H A Dhibernate_asm.S62 /* Use MMU Bypass */
/linux-4.4.14/arch/c6x/include/asm/
H A Dpgtable.h71 * c6x is !MMU, so define the simpliest implementation
/linux-4.4.14/arch/cris/arch-v10/mm/
H A Dfault.c81 * the MMU registers. handle_mmu_bus_fault()
/linux-4.4.14/mm/
H A Dkmemcheck.c32 * Mark it as non-present for the MMU so that our accesses to kmemcheck_alloc_shadow()
/linux-4.4.14/fs/romfs/
H A Dmmap-nommu.c18 * - only supported for NOMMU at the moment (MMU can't doesn't copy private
/linux-4.4.14/arch/powerpc/perf/
H A De6500-pmu.c64 * There are data/instruction MMU misses, but that's a miss on
H A De500-pmu.c65 * There are data/instruction MMU misses, but that's a miss on
/linux-4.4.14/arch/score/include/asm/
H A Dpage.h28 * using MMU this corresponds to the first free page in physical memory (aligned
/linux-4.4.14/arch/sh/include/cpu-sh5/cpu/
H A Dcache.h84 indexing the cache sets and those passed to the MMU for translation. In the
/linux-4.4.14/arch/microblaze/kernel/cpu/
H A Dcpuinfo.c99 * please do not use FULL PVR with MMU */ setup_cpuinfo()
H A Dmb.c74 seq_printf(m, " MMU:\t\t%x\n", cpuinfo.mmu); show_cpuinfo()
/linux-4.4.14/arch/nios2/
H A DMakefile21 export MMU
/linux-4.4.14/arch/nios2/include/asm/
H A Dpage.h5 * MMU support based on asm/page.h from mips which is:
/linux-4.4.14/arch/ia64/include/asm/
H A Dpci.h39 * Platforms with a hardware I/O MMU _must_ turn this off to suppress the
/linux-4.4.14/arch/m32r/mm/
H A Dinit.c36 * Cache of MMU context last used.
/linux-4.4.14/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h333 MMU
344 #define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
346 usable for an MMU-based OS */
/linux-4.4.14/arch/m68k/sun3/
H A Dmmu_emu.c2 ** Tablewalk MMU emulator
124 * Initialise the MMU emulator.
402 /* Write the pte value to hardware MMU */ mmu_emu_handle_fault()
/linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/
H A Dnv04.c72 * MMU subdev
H A Dnv41.c85 * MMU subdev
/linux-4.4.14/arch/sh/kernel/cpu/shmobile/
H A Dpm.c61 /* flush the caches if MMU flag is set */ sh_mobile_call_standby()
/linux-4.4.14/arch/cris/include/arch-v32/arch/
H A Dmmu.h4 /* MMU context type. */
/linux-4.4.14/arch/hexagon/include/asm/
H A Dpgtable.h58 * the PTE describes MMU programming or swap space.
184 * For now, assume that higher-level code will do TLB/MMU invalidations
203 * For the Hexagon Virtual Machine MMU (or its emulation), a null/invalid
419 * VM may require a virtual instruction to alert the MMU.
H A Dvm_mmu.h28 * Virtual machine MMU allows first-level entries to either be

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