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Searched refs:LR (Results 1 – 37 of 37) sorted by relevance

/linux-4.4.14/drivers/video/fbdev/matrox/
Dmatroxfb_maven.c522 #define LR(x) maven_set_reg(c, (x), m->regs[(x)]) macro
547 LR(0x00); LR(0x01); LR(0x02); LR(0x03); in maven_init_TV()
549 LR(0x04); in maven_init_TV()
551 LR(0x2C); in maven_init_TV()
552 LR(0x08); in maven_init_TV()
553 LR(0x0A); in maven_init_TV()
554 LR(0x09); in maven_init_TV()
555 LR(0x29); in maven_init_TV()
558 LR(0x0B); in maven_init_TV()
559 LR(0x0C); in maven_init_TV()
[all …]
Dmatroxfb_g450.c502 #define LR(x) cve2_set_reg(minfo, (x), m->regs[(x)]) macro
508 LR(0x80); in cve2_init_TV()
509 LR(0x82); LR(0x83); in cve2_init_TV()
510 LR(0x84); LR(0x85); in cve2_init_TV()
515 LR(i); in cve2_init_TV()
/linux-4.4.14/tools/perf/arch/arm/tests/
Dregs_load.S17 #define LR 0x70 macro
54 str lr, [r0, #LR]
/linux-4.4.14/Documentation/virtual/kvm/arm/
Dvgic-mapped-irqs.txt32 Registers (LRs) on the GIC before running a VCPU. The LR is programmed
35 interrupt, the LR state moves from Pending to Active, and finally to
39 KVM must also program an additional field in the LR, the physical IRQ
57 - KVM sets the LR.Pending bit, because this is the only way the GICV
59 - LR.Pending will stay set as long as the guest has not acked the interrupt.
60 - LR.Pending transitions to LR.Active on the guest read of the IAR, as
63 but the LR.Active is left untouched (set).
64 - KVM clears the LR on VM exits when the physical distributor
106 to queue the pending state onto the LR, even though the guest won't use
133 necessary, and queue the pending state onto the LR.
/linux-4.4.14/arch/arm/kernel/
Dunwind.c88 LR = 14, enumerator
353 ctrl->vrs[PC] = ctrl->vrs[LR]; in unwind_exec_insn()
378 ctrl->vrs[FP], ctrl->vrs[SP], ctrl->vrs[LR], ctrl->vrs[PC]); in unwind_exec_insn()
412 ctrl.vrs[LR] = frame->lr; in unwind_frame()
457 ctrl.vrs[PC] = ctrl.vrs[LR]; in unwind_frame()
465 frame->lr = ctrl.vrs[LR]; in unwind_frame()
Dentry-header.S171 @ Store/load the USER SP and LR registers by switching to the SYS
Dentry-armv.S275 ldrh r0, [r4, #-2] @ Thumb instruction at LR - 2
/linux-4.4.14/Documentation/devicetree/bindings/display/panel/
Dsharp,ls037v7dw01.txt14 ordered MO, LR, and UD as specified in the LS037V7DW01.pdf file.
35 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
/linux-4.4.14/arch/powerpc/kernel/
Dswsusp_asm64.S89 SAVE_SPECIAL(LR)
136 RESTORE_SPECIAL(LR)
270 RESTORE_SPECIAL(LR)
/linux-4.4.14/Documentation/networking/
Dixgbe.txt49 LR Modules
50 Intel DUAL RATE 1G/10G SFP+ LR (bailed) FTLX1471D3BCV-IT
51 Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDDZ-IN1
52 Intel DUAL RATE 1G/10G SFP+ LR (bailed) AFCT-701SDZ-IN2
61 Finisar SFP+ LR bailed, 10g single rate FTLX1471D3BCL
65 Finisar DUAL RATE 1G/10G SFP+ LR (No Bail) FTLX1471D3QCV-IT
66 Avago DUAL RATE 1G/10G SFP+ LR (No Bail) AFCT-701SDZ-IN1
88 - LAN on Motherboard (LOMs) may support DA, SR, or LR modules. Other module
98 Finisar SFP+ LR bailed, 10g single rate FTLX1471D3BCL
Dixgb.txt56 82597EX Intel(R) PRO/10GbE LR/SR/CX4 10G Base-LR (1310 nm optical fiber)
/linux-4.4.14/arch/arm/mm/
Dproc-v7m.S104 mov r6, lr @ save LR
111 mov lr, r6 @ restore LR
/linux-4.4.14/tools/perf/arch/arm/util/
Dunwind-libdw.c31 dwarf_regs[14] = REG(LR); in libdw__arch_set_initial_registers()
/linux-4.4.14/arch/arm/lib/
Dbacktrace.S68 bic sv_pc, sv_pc, mask @ mask PC/LR for the mode
78 bic r1, r1, mask @ mask PC/LR for the mode
/linux-4.4.14/net/ieee802154/
DKconfig10 Say Y here to compile LR-WPAN support into the kernel or say M to
/linux-4.4.14/arch/powerpc/platforms/52xx/
Dlite5200_sleep.S68 SAVE_SPRN(LR, 0x1c)
246 LOAD_SPRN(LR, 0x1c)
/linux-4.4.14/arch/m32r/kernel/
Dentry.S109 #define LR(reg) @(0x64,reg) macro
/linux-4.4.14/arch/arm/boot/dts/
Domap3-evm-common.dtsi86 &gpio1 2 GPIO_ACTIVE_HIGH /* gpio2, lcd LR */
/linux-4.4.14/tools/testing/selftests/powerpc/switch_endian/
Dcheck.S25 addi r9,r15,32 # check LR
/linux-4.4.14/arch/m32r/platforms/oaks32r/
Ddot.gdbinit.nommu81 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
/linux-4.4.14/arch/powerpc/platforms/8xx/
DKconfig140 (by not placing conditional branches or branches to LR or CTR
/linux-4.4.14/arch/m32r/platforms/mappi3/
Ddot.gdbinit139 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
/linux-4.4.14/arch/m32r/platforms/mappi2/
Ddot.gdbinit.vdec2150 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
/linux-4.4.14/arch/m32r/platforms/m32700ut/
Ddot.gdbinit_400MHz_32MB151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
Ddot.gdbinit_200MHz_16MB151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
Ddot.gdbinit_300MHz_32MB151 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
/linux-4.4.14/arch/m32r/platforms/mappi/
Ddot.gdbinit167 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
Ddot.gdbinit.nommu167 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$sp
Ddot.gdbinit.smp235 printf "R12[0x%08lX] FP[0x%08lX] LR[0x%08lX] SP[0x%08lX]\n",$r12,$fp,$lr,$fp
/linux-4.4.14/arch/frv/kernel/
Dswitch_to.S115 # - SP, FP, LR, GR15, GR28 and GR29 will have been set up appropriately
/linux-4.4.14/arch/m32r/platforms/opsput/
Ddot.gdbinit176 printf "R12[%08lx] FP[%08lx] LR[%08lx] SP[%08lx]\n",$r12,$fp,$lr,$sp
/linux-4.4.14/Documentation/powerpc/
Dtransactional_memory.txt62 Checkpointed registers include all GPRs, FPRs, VRs/VSRs, LR, CCR/CR, CTR, FPCSR
/linux-4.4.14/Documentation/frv/
Dkernel-ABI.txt131 LR Return address after CALL Clobbered
/linux-4.4.14/scripts/genksyms/
Dparse.tab.c_shipped1276 token list. However, the list is correct for canonical LR with
/linux-4.4.14/scripts/dtc/
Ddtc-parser.tab.c_shipped1078 token list. However, the list is correct for canonical LR with
/linux-4.4.14/scripts/kconfig/
Dzconf.tab.c_shipped1239 token list. However, the list is correct for canonical LR with
/linux-4.4.14/Documentation/s390/
DDebugging390.txt772 0001AFF8' LR 180F CC 0