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Searched refs:HSYNC (Results 1 – 20 of 20) sorted by relevance

/linux-4.4.14/Documentation/devicetree/bindings/media/i2c/
Dtvp514x.txt17 - hsync-active: HSYNC Polarity configuration for endpoint.
Dtvp7002.txt10 - hsync-active: HSYNC Polarity configuration for the bus. Default value when
/linux-4.4.14/drivers/video/fbdev/i810/
Di810_regs.h150 #define HSYNC 0x60008 macro
/linux-4.4.14/Documentation/fb/
Dpxafb.txt27 hsynclen:HSYNC == LCCR1_HSW + 1
45 hsync:HSYNC
Dmatroxfb.txt250 left:X - left boundary: pixels between end of HSYNC pulse and first pixel.
252 right:X - right boundary: pixels between end of picture and start of HSYNC
254 hslen:X - length of HSYNC pulse, in pixels. Default is derived from `vesa'
258 sync:X - sync. pulse - bit 0 inverts HSYNC polarity, bit 1 VSYNC polarity.
259 If bit 3 (value 0x08) is set, composite sync instead of HSYNC is
/linux-4.4.14/Documentation/devicetree/bindings/media/
Dvideo-interfaces.txt83 - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH respectively.
85 Note, that if HSYNC and VSYNC polarities are not specified, embedded
87 - data-active: similar to HSYNC and VSYNC, specifies data line polarity.
/linux-4.4.14/include/video/
Dsstfb.h160 #define HSYNC 0x0220 macro
/linux-4.4.14/Documentation/devicetree/bindings/display/exynos/
Dexynos_dp.txt63 HSYNC polarity configuration.
/linux-4.4.14/arch/arm/boot/dts/
Dimx53-mba53.dts152 /* VGA_VSYNC, HSYNC with max drive strength */
Dam437x-sk-evm.dts362 0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
Dam43x-epos-evm.dts305 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
Dam437x-gp-evm.dts286 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
Dat91sam9g45.dtsi515 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* HSYNC */
/linux-4.4.14/arch/avr32/mach-at32ap/include/mach/
Dat32ap700x.h227 ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) | \
/linux-4.4.14/drivers/gpu/drm/i2c/
Dch7006_mode.c122 .flags = DRM_MODE_FLAG_##hsynp##HSYNC | \
/linux-4.4.14/drivers/pinctrl/sh-pfc/
Dpfc-sh7786.c528 GPIO_FN(HSYNC),
/linux-4.4.14/drivers/gpu/drm/
Ddrm_modes.c1024 MODE_STATUS(HSYNC),
/linux-4.4.14/drivers/video/fbdev/
Dsstfb.c533 sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1)); in sstfb_set_par()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_display.c4082 I915_READ(HSYNC(cpu_transcoder))); in ironlake_pch_transcoder_set_timings()
7734 I915_WRITE(HSYNC(cpu_transcoder), in intel_set_pipe_timings()
7778 tmp = I915_READ(HSYNC(cpu_transcoder)); in intel_get_pipe_timings()
10680 int hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_crtc_mode_get()
15744 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); in intel_display_capture_error_state()
Di915_reg.h3039 #define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A) macro