Searched refs:HALT (Results 1 – 9 of 9) sorted by relevance
| /linux-4.4.14/arch/arm/mach-clps711x/include/mach/ |
| D | clps711x.h | 56 #define HALT (0x0800) macro
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| /linux-4.4.14/arch/arm/mach-clps711x/ |
| D | devices.c | 25 DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128);
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| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | vi.c | 736 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); in vi_gpu_soft_reset()
742 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); in vi_gpu_soft_reset()
886 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); in vi_gpu_pci_config_reset()
891 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 1); in vi_gpu_pci_config_reset()
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| D | sdma_v2_4.c | 425 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_enable()
427 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v2_4_enable()
1137 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
1144 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v2_4_soft_reset()
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| D | sdma_v3_0.c | 561 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_enable()
563 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); in sdma_v3_0_enable()
1299 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_soft_reset()
1306 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0); in sdma_v3_0_soft_reset()
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| /linux-4.4.14/arch/mips/dec/ |
| D | int-handler.S | 221 FEXPORT(cpu_all_int) # HALT, timers, software junk
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| /linux-4.4.14/arch/arc/kernel/ |
| D | entry-compact.S | 387 ; If this does happen we simply HALT as it means a BUG !!!
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| /linux-4.4.14/Documentation/s390/ |
| D | cds.txt | 157 ccw_device_halt() function. Some devices require to initially issue a HALT
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| D | Debugging390.txt | 1316 (CLEAR SUBCHANNEL, HALT SUBCHANNEL, MODIFY SUBCHANNEL, RESUME SUBCHANNEL,
1320 completed successfully) and HALT SUBCHANNEL (to kill IO). A subchannel can have
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