Searched refs:GPDR (Results 1 – 19 of 19) sorted by relevance
188 GPDR &= ~BADGE4_GPIO_INT_VID; in badge4_init()189 GPDR |= (BADGE4_GPIO_LGP2 | BADGE4_GPIO_LGP3 | in badge4_init()198 GPDR |= (BADGE4_GPIO_SDSDA | BADGE4_GPIO_SDSCL); in badge4_init()202 GPDR |= (BADGE4_GPIO_UART_HS1 | BADGE4_GPIO_UART_HS2); in badge4_init()206 GPDR |= BADGE4_GPIO_MUXSEL0; in badge4_init()209 GPDR &= ~(BADGE4_GPIO_TESTPT_J5 | BADGE4_GPIO_TESTPT_J6); in badge4_init()211 GPDR |= BADGE4_GPIO_TESTPT_J7; in badge4_init()215 GPDR |= BADGE4_GPIO_PCMEN5V; in badge4_init()
132 GPDR &= ~SDA; in adv7171_send()140 GPDR |= SDA; in adv7171_send()146 unsigned gpdr = GPDR; in adv7171_write()153 GPDR = (GPDR | SCK | MOD) & ~SDA; in adv7171_write()157 GPDR |= SDA; in adv7171_write()168 GPDR = gpdr; in adv7171_write()428 GPDR |= GPIO_GPIO16; in assabet_init()437 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; in assabet_init()445 GPDR |= GPIO_GPIO27; in assabet_init()523 GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ in get_assabet_scr()[all …]
119 GPDR |= GPIO_UART_TXD; in pleb_map_io()120 GPDR &= ~GPIO_UART_RXD; in pleb_map_io()131 GPDR |= GPIO_ETH0_EN; /* set to output */ in pleb_map_io()134 GPDR &= ~GPIO_ETH0_IRQ; in pleb_map_io()
62 SAVE(GPDR); in sa11x0_pm_enter()96 RESTORE(GPDR); in sa11x0_pm_enter()
91 GPDR |= GPIO_UART_TXD | SHANNON_GPIO_CODEC_RESET; in shannon_map_io()92 GPDR &= ~GPIO_UART_RXD; in shannon_map_io()
407 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; in sa1110_mb_disable()426 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; in sa1110_mb_enable()
182 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; in pci_nanoengine_setup()
45 GPDR |= GPIO_32_768kHz; in clk_gpio27_enable()52 GPDR &= ~GPIO_32_768kHz; in clk_gpio27_disable()
160 GPDR |= GPIO_UART_TXD; in lart_map_io()161 GPDR &= ~GPIO_UART_RXD; in lart_map_io()
214 GPDR |= GPIO_UART_TXD | GPIO_LDD13 | GPIO_LDD15; in simpad_map_io()215 GPDR &= ~GPIO_UART_RXD; in simpad_map_io()
156 GPDR |= CERF_GPIO_CF_RESET; in cerf_map_io()
244 GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */ in jornada720_init()
315 GPDR = 0; /* Configure all GPIOs as input */ in h3xxx_map_io()
364 GPDR = GPIO_LDD8 | GPIO_LDD9 | GPIO_LDD10 | GPIO_LDD11 | GPIO_LDD12 | in collie_init()
35 #define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c) macro77 GPDR(gpio) |= mask; in __mfp_config_gpio()79 GPDR(gpio) &= ~mask; in __mfp_config_gpio()361 (GPDR(i) & GPIO_bit(i))) { in pxa2xx_mfp_suspend()372 saved_gpdr[i] = GPDR(i * 32); in pxa2xx_mfp_suspend()385 GPDR(i) |= GPIO_bit(i); in pxa2xx_mfp_suspend()387 GPDR(i) &= ~GPIO_bit(i); in pxa2xx_mfp_suspend()402 GPDR(i * 32) = saved_gpdr[i]; in pxa2xx_mfp_resume()435 gpdr_lpm[i] = GPDR(i * 32); in pxa2xx_mfp_init()
36 GPDR &= ~GPIO_GPIO(offset); in sa1100_direction_input()47 GPDR |= GPIO_GPIO(offset); in sa1100_direction_output()
55 GPDR, /* pin direction */ enumerator142 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in intel_gpio_direction_input()165 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in intel_gpio_direction_output()
1105 #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */ macro
776 GPDR |= mask; in sa1100fb_setup_gpio()