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Searched refs:GEN7_MISCCPCTL (Results 1 – 6 of 6) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_guc_loader.c341 I915_WRITE(GEN7_MISCCPCTL, (GEN8_DOP_CLOCK_GATE_GUC_ENABLE | in guc_ucode_xfer()
342 I915_READ(GEN7_MISCCPCTL))); in guc_ucode_xfer()
Di915_drv.c1177 s->misccpctl = I915_READ(GEN7_MISCCPCTL); in vlv_save_gunit_s0ix_state()
1259 I915_WRITE(GEN7_MISCCPCTL, s->misccpctl); in vlv_restore_gunit_s0ix_state()
Di915_irq.c1186 misccpctl = I915_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1187 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivybridge_parity_work()
1188 POSTING_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
1228 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in ivybridge_parity_work()
Dintel_ringbuffer.c1117 I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & in bxt_init_workarounds()
Dintel_pm.c6622 misccpctl = I915_READ(GEN7_MISCCPCTL); in broadwell_init_clock_gating()
6623 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in broadwell_init_clock_gating()
6631 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in broadwell_init_clock_gating()
Di915_reg.h6961 #define GEN7_MISCCPCTL (0x9424) macro