Searched refs:DP_TRAIN_PRE_EMPHASIS_MASK (Results 1 – 6 of 6) sorted by relevance
238 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in amdgpu_atombios_dp_get_adjust_train()665 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in amdgpu_atombios_dp_link_train_cr()718 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in amdgpu_atombios_dp_link_train_ce()
289 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]); in dp_get_adjust_train()756 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >> in radeon_dp_link_train_cr()807 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in radeon_dp_link_train_ce()
268 # define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) macro
3160 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels()3249 return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 && in chv_need_uniq_trans_scale()3265 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_signal_levels()3473 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in gen4_signal_levels()3496 DP_TRAIN_PRE_EMPHASIS_MASK); in gen6_edp_signal_levels()3524 DP_TRAIN_PRE_EMPHASIS_MASK); in gen7_edp_signal_levels()3588 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> in intel_dp_set_signal_levels()
2269 DP_TRAIN_PRE_EMPHASIS_MASK); in ddi_signal_levels()
1325 if (p == DP_TRAIN_PRE_EMPHASIS_MASK) in cdv_intel_get_adjust_train()1445 premph = ((signal_level & DP_TRAIN_PRE_EMPHASIS_MASK)) >> in cdv_intel_dp_set_vswing_premph()