Searched refs:DP_TP_CTL (Results 1 – 3 of 3) sorted by relevance
645 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()688 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()703 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()706 I915_WRITE(DP_TP_CTL(PORT_E), temp); in hsw_fdi_link_train()707 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()2378 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_post_disable()2381 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_post_disable()3047 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { in intel_ddi_prepare_link_retrain()3055 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()3058 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()[all …]
2471 uint32_t temp = I915_READ(DP_TP_CTL(port)); in _intel_dp_set_link_train()2494 I915_WRITE(DP_TP_CTL(port), temp); in _intel_dp_set_link_train()3669 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()3672 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
7219 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) macro