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Searched refs:DPLL (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/Documentation/devicetree/bindings/clock/ti/
Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
39 - reg : offsets for the register set for controlling the DPLL.
49 - DPLL mode setting - defining any one or more of the following overrides
51 - ti,low-power-stop : DPLL supports low power stop mode, gating output
52 - ti,low-power-bypass : DPLL output matches rate of parent bypass clock
53 - ti,lock : DPLL locks in programmed rate
Dapll.txt11 a subtype of a DPLL [2], although a simplified one at that.
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_dvo.c488 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
489 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init()
496 I915_WRITE(DPLL(pipe), dpll[pipe]); in intel_dvo_init()
Dintel_runtime_pm.c877 u32 val = I915_READ(DPLL(pipe)); in vlv_display_power_well_init()
883 I915_WRITE(DPLL(pipe), val); in vlv_display_power_well_init()
1044 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1954 uint32_t status = I915_READ(DPLL(PIPE_A)); in chv_phy_control_init()
Dintel_dsi.c484 tmp = I915_READ(DPLL(pipe)); in intel_dsi_pre_enable()
486 I915_WRITE(DPLL(pipe), tmp); in intel_dsi_pre_enable()
Dintel_display.c1164 val = I915_READ(DPLL(pipe)); in assert_pll()
1603 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1692 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1773 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1775 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
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Di915_reg.h2204 #define DPLL(pipe) _PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) macro
Dintel_dp.c333 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
/linux-4.4.14/arch/arm/mach-omap2/
Dsleep24xx.S74 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
/linux-4.4.14/Documentation/devicetree/bindings/phy/
Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
/linux-4.4.14/Documentation/arm/OMAP/
DDSS31 - Use DSI DPLL to create DSS FCK
293 Using DSI DPLL to generate pixel clock it is possible produce the pixel clock
/linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
Dreg.h281 #define DPLL 0x034A macro
/linux-4.4.14/Documentation/networking/
Dz8530drv.txt291 present at all (BayCom). It feeds back the output of the DPLL