Lines Matching refs:DPLL
1164 val = I915_READ(DPLL(pipe)); in assert_pll()
1603 int reg = DPLL(crtc->pipe); in vlv_enable_pll()
1665 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); in chv_enable_pll()
1668 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) in chv_enable_pll()
1692 int reg = DPLL(crtc->pipe); in i9xx_enable_pll()
1713 I915_WRITE(DPLL(!crtc->pipe), in i9xx_enable_pll()
1714 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); in i9xx_enable_pll()
1773 I915_WRITE(DPLL(PIPE_B), in i9xx_disable_pll()
1774 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1775 I915_WRITE(DPLL(PIPE_A), in i9xx_disable_pll()
1776 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); in i9xx_disable_pll()
1787 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); in i9xx_disable_pll()
1788 POSTING_READ(DPLL(pipe)); in i9xx_disable_pll()
1805 I915_WRITE(DPLL(pipe), val); in vlv_disable_pll()
1806 POSTING_READ(DPLL(pipe)); in vlv_disable_pll()
1823 I915_WRITE(DPLL(pipe), val); in chv_disable_pll()
1824 POSTING_READ(DPLL(pipe)); in chv_disable_pll()
1846 dpll_reg = DPLL(0); in vlv_wait_port_ready()
1850 dpll_reg = DPLL(0); in vlv_wait_port_ready()
7435 int dpll_reg = DPLL(crtc->pipe); in chv_prepare_pll()
8180 tmp = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
8190 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); in i9xx_get_pipe_config()
10698 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); in intel_crtc_mode_get()