Searched refs:CHCR (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/arch/sh/drivers/dma/
H A Ddma-sh.c85 * We determine the correct shift size based off of the CHCR transmit size
96 u32 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); calc_xmit_shift()
114 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); dma_tei()
120 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); dma_tei()
154 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); sh_dmac_configure_channel()
165 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); sh_dmac_enable_dma()
171 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); sh_dmac_enable_dma()
189 chcr = __raw_readl(dma_base_addr(chan->chan) + CHCR); sh_dmac_disable_dma()
191 __raw_writel(chcr, (dma_base_addr(chan->chan) + CHCR)); sh_dmac_disable_dma()
237 if (!(__raw_readl(dma_base_addr(chan->chan) + CHCR) & CHCR_DE)) sh_dmac_get_dma_residue()
/linux-4.4.14/arch/sh/include/cpu-sh3/cpu/
H A Ddma-register.h22 * with their respective values as they appear in the CHCR registers.
/linux-4.4.14/arch/sh/include/cpu-sh4/cpu/
H A Ddma-register.h43 /* Transmit sizes and respective CHCR register values */
79 /* Transmit sizes and respective CHCR register values */
/linux-4.4.14/drivers/dma/sh/
H A Dshdma-arm.h16 /* Transmit sizes and respective CHCR register values */
H A Dshdmac.c45 #define CHCR 0x0C /* Channel Control Register */ macro
251 /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */ dmae_set_chcr()
777 shdev->chcr_offset = CHCR; sh_dmae_probe()
H A Drcar-dmac.c130 * @lock: protects the channel CHCR register and the desc members
/linux-4.4.14/include/linux/
H A Dsh_dma.h65 * @chcr_offset: CHCR address offset
66 * @chcr_ie_bit: CHCR Interrupt Enable bit
/linux-4.4.14/arch/sh/include/asm/
H A Ddma-register.h20 #define CHCR 0x0C /* Channel Control Register */ macro

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