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Searched refs:BLC_PWM_CTL2 (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/gma500/
Doaktrail_device.c94 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in oaktrail_set_brightness()
135 REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2))); in device_backlight_init()
247 regs->saveBLC_PWM_CTL2 = PSB_RVDC32(BLC_PWM_CTL2); in oaktrail_save_display_registers()
371 PSB_WVDC32(regs->saveBLC_PWM_CTL2, BLC_PWM_CTL2); in oaktrail_restore_display_registers()
Dcdv_device.c86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE; in cdv_backlight_combination_mode()
290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2); in cdv_save_display_registers()
358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2); in cdv_restore_display_registers()
Dcdv_intel_lvds.c766 pwm = REG_READ(BLC_PWM_CTL2); in cdv_intel_lvds_init()
772 REG_WRITE(BLC_PWM_CTL2, pwm); in cdv_intel_lvds_init()
Dpsb_intel_reg.h93 #define BLC_PWM_CTL2 0x61250 macro
Dcdv_intel_dp.c2076 pwm_ctrl = REG_READ(BLC_PWM_CTL2); in cdv_intel_dp_init()
2078 REG_WRITE(BLC_PWM_CTL2, pwm_ctrl); in cdv_intel_dp_init()
/linux-4.4.14/drivers/gpu/drm/i915/
Dintel_panel.c781 tmp = I915_READ(BLC_PWM_CTL2); in i965_disable_backlight()
782 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); in i965_disable_backlight()
987 ctl2 = I915_READ(BLC_PWM_CTL2); in i965_enable_backlight()
991 I915_WRITE(BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
1006 I915_WRITE(BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
1007 POSTING_READ(BLC_PWM_CTL2); in i965_enable_backlight()
1008 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); in i965_enable_backlight()
1544 ctl2 = I915_READ(BLC_PWM_CTL2); in i965_setup_backlight()
Di915_reg.h3578 #define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */ macro