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Searched refs:BIT_ULL (Results 1 – 35 of 35) sorted by relevance

/linux-4.4.14/drivers/net/ethernet/cavium/thunder/
Dthunder_bgx.h25 #define CMR_PKT_TX_EN BIT_ULL(13)
26 #define CMR_PKT_RX_EN BIT_ULL(14)
27 #define CMR_EN BIT_ULL(15)
29 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
45 #define RX_DMACX_CAM_EN BIT_ULL(48)
74 #define SPU_CTL_LOW_POWER BIT_ULL(11)
75 #define SPU_CTL_LOOPBACK BIT_ULL(14)
76 #define SPU_CTL_RESET BIT_ULL(15)
78 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
80 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
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Dnicvf_queues.h117 #define NICVF_SQ_EN BIT_ULL(19)
120 #define NICVF_CQ_RESET BIT_ULL(41)
121 #define NICVF_SQ_RESET BIT_ULL(17)
122 #define NICVF_RBDR_RESET BIT_ULL(43)
Dnic_main.c104 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf)); in nic_clear_mbx_intr()
/linux-4.4.14/drivers/net/ethernet/cavium/liquidio/
Dcn66xx_regs.h372 #define CN6XXX_INTR_DMA0_FORCE BIT_ULL(32)
373 #define CN6XXX_INTR_DMA1_FORCE BIT_ULL(33)
374 #define CN6XXX_INTR_DMA0_COUNT BIT_ULL(34)
375 #define CN6XXX_INTR_DMA1_COUNT BIT_ULL(35)
376 #define CN6XXX_INTR_DMA0_TIME BIT_ULL(36)
377 #define CN6XXX_INTR_DMA1_TIME BIT_ULL(37)
378 #define CN6XXX_INTR_INSTR_DB_OF_ERR BIT_ULL(48)
379 #define CN6XXX_INTR_SLIST_DB_OF_ERR BIT_ULL(49)
380 #define CN6XXX_INTR_POUT_ERR BIT_ULL(50)
381 #define CN6XXX_INTR_PIN_BP_ERR BIT_ULL(51)
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Dcn68xx_regs.h49 #define CN68XX_INTR_PIPE_ERR BIT_ULL(61)
/linux-4.4.14/drivers/net/ethernet/intel/i40evf/
Di40e_txrx.h81 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
82 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
83 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
84 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
85 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
86 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
87 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
88 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
89 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
90 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
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Di40evf_ethtool.c384 if (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP)) in i40evf_get_rss_hash_opts()
388 if (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP)) in i40evf_get_rss_hash_opts()
400 if (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP)) in i40evf_get_rss_hash_opts()
404 if (hena & BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP)) in i40evf_get_rss_hash_opts()
482 hena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP); in i40evf_set_rss_hash_opt()
485 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP); in i40evf_set_rss_hash_opt()
494 hena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP); in i40evf_set_rss_hash_opt()
497 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP); in i40evf_set_rss_hash_opt()
506 hena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | in i40evf_set_rss_hash_opt()
507 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4)); in i40evf_set_rss_hash_opt()
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Di40e_type.h667 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
801 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
977 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
982 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
995 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1077 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
Di40e_hmc.h131 val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
150 val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
/linux-4.4.14/drivers/net/ethernet/intel/i40e/
Di40e_txrx.h81 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
82 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
83 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
84 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
85 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
86 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
87 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
88 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
89 BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
90 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
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Di40e.h300 #define I40E_FLAG_RX_CSUM_ENABLED BIT_ULL(1)
301 #define I40E_FLAG_MSI_ENABLED BIT_ULL(2)
302 #define I40E_FLAG_MSIX_ENABLED BIT_ULL(3)
303 #define I40E_FLAG_RX_1BUF_ENABLED BIT_ULL(4)
304 #define I40E_FLAG_RX_PS_ENABLED BIT_ULL(5)
305 #define I40E_FLAG_RSS_ENABLED BIT_ULL(6)
306 #define I40E_FLAG_VMDQ_ENABLED BIT_ULL(7)
307 #define I40E_FLAG_FDIR_REQUIRES_REINIT BIT_ULL(8)
308 #define I40E_FLAG_NEED_LINK_UPDATE BIT_ULL(9)
309 #define I40E_FLAG_IWARP_ENABLED BIT_ULL(10)
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Di40e_type.h547 #define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
680 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
814 #define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
990 #define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
995 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1008 #define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1090 #define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1099 #define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
Di40e_hmc.h131 val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
150 val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
Di40e_ethtool.c2167 hena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP); in i40e_set_rss_hash_opt()
2170 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP); in i40e_set_rss_hash_opt()
2179 hena &= ~BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP); in i40e_set_rss_hash_opt()
2182 hena |= BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP); in i40e_set_rss_hash_opt()
2191 hena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | in i40e_set_rss_hash_opt()
2192 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4)); in i40e_set_rss_hash_opt()
2195 hena |= (BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | in i40e_set_rss_hash_opt()
2196 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4)); in i40e_set_rss_hash_opt()
2205 hena &= ~(BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | in i40e_set_rss_hash_opt()
2206 BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6)); in i40e_set_rss_hash_opt()
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Di40e_lan_hmc.c132 obj->size = BIT_ULL(size_exp); in i40e_init_lan_hmc()
155 obj->size = BIT_ULL(size_exp); in i40e_init_lan_hmc()
178 obj->size = BIT_ULL(size_exp); in i40e_init_lan_hmc()
201 obj->size = BIT_ULL(size_exp); in i40e_init_lan_hmc()
908 mask = BIT_ULL(ce_info->width) - 1; in i40e_write_qword()
Di40e_main.c573 *stat = (new_data + BIT_ULL(48)) - *offset; in i40e_stat_update48()
596 *stat = (u32)((new_data + BIT_ULL(32)) - *offset); in i40e_stat_update32()
1593 if (enabled_tc & BIT_ULL(i)) /* TC is enabled */ in i40e_vsi_setup_queue_map()
1622 if (vsi->tc_config.enabled_tc & BIT_ULL(i)) { in i40e_vsi_setup_queue_map()
1649 while (num_qps && (BIT_ULL(pow) < qcount)) { in i40e_vsi_setup_queue_map()
2973 BIT_ULL(I40E_RXQ_CTX_HBUFF_SHIFT)); in i40e_vsi_configure_rx()
2975 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT)); in i40e_vsi_configure_rx()
3005 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n))) in i40e_vsi_config_dcb_rings()
4444 enabled_tc |= BIT_ULL(tc); in i40e_get_iscsi_tc_map()
4528 if (enabled_tc & BIT_ULL(i)) in i40e_pf_get_num_tc()
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Di40e_virtchnl_pf.c1050 BIT_ULL(__I40E_PF_RESET_REQUESTED)); in i40e_pci_sriov_configure()
1058 i40e_do_reset_safe(pf, BIT_ULL(__I40E_PF_RESET_REQUESTED)); in i40e_pci_sriov_configure()
Di40e_debugfs.c1016 BIT_ULL(__I40E_PF_RESET_REQUESTED)); in i40e_dbg_command_write()
/linux-4.4.14/arch/x86/include/asm/
Dperf_event.h162 #define GLOBAL_STATUS_COND_CHG BIT_ULL(63)
163 #define GLOBAL_STATUS_BUFFER_OVF BIT_ULL(62)
164 #define GLOBAL_STATUS_UNC_OVF BIT_ULL(61)
165 #define GLOBAL_STATUS_ASIF BIT_ULL(60)
166 #define GLOBAL_STATUS_COUNTERS_FROZEN BIT_ULL(59)
167 #define GLOBAL_STATUS_LBRS_FROZEN BIT_ULL(58)
168 #define GLOBAL_STATUS_TRACE_TOPAPMI BIT_ULL(55)
Dmsr-index.h76 #define LBR_INFO_MISPRED BIT_ULL(63)
77 #define LBR_INFO_IN_TX BIT_ULL(62)
78 #define LBR_INFO_ABORT BIT_ULL(61)
/linux-4.4.14/drivers/ntb/hw/intel/
Dntb_hw_intel.h147 #define XEON_DB_LINK_BIT BIT_ULL(XEON_DB_LINK)
193 #define ATOM_DB_VALID_MASK (BIT_ULL(ATOM_DB_COUNT) - 1)
240 #define NTB_HWERR_SDOORBELL_LOCKUP BIT_ULL(0)
241 #define NTB_HWERR_SB01BASE_LOCKUP BIT_ULL(1)
242 #define NTB_HWERR_B2BDOORBELL_BIT14 BIT_ULL(2)
245 #define NTB_UNSAFE_DB BIT_ULL(0)
246 #define NTB_UNSAFE_SPAD BIT_ULL(1)
Dntb_hw_intel.c338 mask = BIT_ULL(shift) - 1; in ndev_vec_mask()
1352 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; in atom_init_ntb()
1823 ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1; in xeon_init_ntb()
/linux-4.4.14/arch/x86/kernel/cpu/
Dperf_event_intel.c276 #define SKL_DEMAND_DATA_RD BIT_ULL(0)
277 #define SKL_DEMAND_RFO BIT_ULL(1)
278 #define SKL_ANY_RESPONSE BIT_ULL(16)
279 #define SKL_SUPPLIER_NONE BIT_ULL(17)
280 #define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
281 #define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
282 #define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
283 #define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
288 #define SKL_SPL_HIT BIT_ULL(30)
289 #define SKL_SNOOP_NONE BIT_ULL(31)
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/linux-4.4.14/arch/powerpc/platforms/powernv/
Dopal-irqchip.c64 if (BIT_ULL(hwirq) & mask) { in opal_handle_events()
70 events &= ~BIT_ULL(hwirq); in opal_handle_events()
/linux-4.4.14/include/linux/
Dvirtio_config.h101 return vdev->features & BIT_ULL(fbit); in __virtio_test_bit()
118 vdev->features |= BIT_ULL(fbit); in __virtio_set_bit()
135 vdev->features &= ~BIT_ULL(fbit); in __virtio_clear_bit()
Dbitops.h7 #define BIT_ULL(nr) (1ULL << (nr)) macro
/linux-4.4.14/drivers/ntb/
Dntb_transport.c774 if (qp_bitmap_alloc & BIT_ULL(i)) { in ntb_transport_link_cleanup()
1071 qp_bitmap &= BIT_ULL(qp_count) - 1; in ntb_transport_probe()
1145 if (qp_bitmap_alloc & BIT_ULL(i)) in ntb_transport_free()
1392 } else if (ntb_db_read(qp->ndev) & BIT_ULL(qp->qp_num)) { in ntb_transport_rxc_db()
1394 ntb_db_clear(qp->ndev, BIT_ULL(qp->qp_num)); in ntb_transport_rxc_db()
1414 ntb_peer_db_set(qp->ndev, BIT_ULL(qp->qp_num)); in ntb_tx_copy_callback()
1634 qp_bit = BIT_ULL(qp->qp_num); in ntb_transport_create_queue()
1759 qp_bit = BIT_ULL(qp->qp_num); in ntb_transport_free_queue()
2040 db_bits &= ~BIT_ULL(qp_num); in ntb_transport_doorbell_callback()
/linux-4.4.14/fs/proc/
Dtask_mmu.c1008 #define PM_SOFT_DIRTY BIT_ULL(55)
1009 #define PM_MMAP_EXCLUSIVE BIT_ULL(56)
1010 #define PM_FILE BIT_ULL(61)
1011 #define PM_SWAP BIT_ULL(62)
1012 #define PM_PRESENT BIT_ULL(63)
/linux-4.4.14/virt/kvm/arm/
Dvgic-v3.c37 #define ICH_LR_VIRTUALID_MASK (BIT_ULL(32) - 1)
/linux-4.4.14/drivers/misc/mic/scif/
Dscif_rma.h64 #define SCIF_REMOTE_FENCE BIT_ULL(SCIF_REMOTE_FENCE_BIT)
/linux-4.4.14/drivers/dma/
Dxgene-dma.c122 #define XGENE_DMA_DESC_NV_BIT BIT_ULL(50)
123 #define XGENE_DMA_DESC_IN_BIT BIT_ULL(55)
124 #define XGENE_DMA_DESC_C_BIT BIT_ULL(63)
125 #define XGENE_DMA_DESC_DR_BIT BIT_ULL(61)
/linux-4.4.14/drivers/powercap/
Dintel_rapl.c45 #define POWER_LIMIT2_ENABLE BIT_ULL(47)
46 #define POWER_LIMIT2_CLAMP BIT_ULL(48)
47 #define POWER_PACKAGE_LOCK BIT_ULL(63)
/linux-4.4.14/net/rds/
Dib.h31 #define RDS_IB_SEND_OP BIT_ULL(63)
/linux-4.4.14/drivers/irqchip/
Dirq-gic-v3-its.c184 cmd->raw_cmd[0] &= BIT_ULL(32) - 1; in its_encode_devid()
/linux-4.4.14/arch/mips/include/asm/
Dmipsregs.h615 #define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)