Lines Matching refs:BIT_ULL
25 #define CMR_PKT_TX_EN BIT_ULL(13)
26 #define CMR_PKT_RX_EN BIT_ULL(14)
27 #define CMR_EN BIT_ULL(15)
29 #define CMR_GLOBAL_CFG_FCS_STRIP BIT_ULL(6)
45 #define RX_DMACX_CAM_EN BIT_ULL(48)
74 #define SPU_CTL_LOW_POWER BIT_ULL(11)
75 #define SPU_CTL_LOOPBACK BIT_ULL(14)
76 #define SPU_CTL_RESET BIT_ULL(15)
78 #define SPU_STATUS1_RCV_LNK BIT_ULL(2)
80 #define SPU_STATUS2_RCVFLT BIT_ULL(10)
82 #define SPU_BX_STATUS_RX_ALIGN BIT_ULL(12)
84 #define SPU_BR_STATUS_BLK_LOCK BIT_ULL(0)
85 #define SPU_BR_STATUS_RCV_LNK BIT_ULL(12)
87 #define SPU_PMD_CRTL_TRAIN_EN BIT_ULL(1)
92 #define SPU_FEC_CTL_FEC_EN BIT_ULL(0)
93 #define SPU_FEC_CTL_ERR_EN BIT_ULL(1)
95 #define SPU_AN_CTL_AN_EN BIT_ULL(12)
96 #define SPU_AN_CTL_XNP_EN BIT_ULL(13)
99 #define SPU_MISC_CTL_INTLV_RDISP BIT_ULL(10)
100 #define SPU_MISC_CTL_RX_DIS BIT_ULL(12)
106 #define SPU_DBG_CTL_AN_ARB_LINK_CHK_EN BIT_ULL(18)
107 #define SPU_DBG_CTL_AN_NONCE_MCT_DIS BIT_ULL(29)
114 #define SMU_TX_APPEND_FCS_D BIT_ULL(2)
118 #define SMU_TX_CTL_DIC_EN BIT_ULL(0)
119 #define SMU_TX_CTL_UNI_EN BIT_ULL(1)
123 #define SMU_CTL_RX_IDLE BIT_ULL(0)
124 #define SMU_CTL_TX_IDLE BIT_ULL(1)
127 #define PCS_MRX_CTL_RST_AN BIT_ULL(9)
128 #define PCS_MRX_CTL_PWR_DN BIT_ULL(11)
129 #define PCS_MRX_CTL_AN_EN BIT_ULL(12)
130 #define PCS_MRX_CTL_LOOPBACK1 BIT_ULL(14)
131 #define PCS_MRX_CTL_RESET BIT_ULL(15)
133 #define PCS_MRX_STATUS_AN_CPT BIT_ULL(5)
137 #define PCS_MISC_CTL_GMX_ENO BIT_ULL(11)
140 #define GMI_PORT_CFG_SPEED BIT_ULL(1)
141 #define GMI_PORT_CFG_DUPLEX BIT_ULL(2)
142 #define GMI_PORT_CFG_SLOT_TIME BIT_ULL(3)
143 #define GMI_PORT_CFG_SPEED_MSB BIT_ULL(8)