| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 54 #define BIT6 0x00000040 macro
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| H A D | halbtc8723b2ant.h | 34 #define BT_INFO_8723B_2ANT_B_A2DP BIT6
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| H A D | halbtc8821a2ant.h | 31 #define BT_INFO_8821A_2ANT_B_A2DP BIT6
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| H A D | halbtc8192e2ant.h | 31 #define BT_INFO_8192E_2ANT_B_A2DP BIT6
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| H A D | halbtc8723b1ant.h | 31 #define BT_INFO_8723B_1ANT_B_A2DP BIT6
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| H A D | halbtc8821a1ant.h | 33 #define BT_INFO_8821A_1ANT_B_A2DP BIT6
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| H A D | halbtcoutsrc.h | 107 #define ALGO_TRACE_FW_EXEC BIT6
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| H A D | halbtc8723b1ant.c | 891 real_byte5 &= ~BIT6; halbtc8723b1ant_set_fw_ps_tdma()
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| /linux-4.4.14/drivers/video/fbdev/via/ |
| H A D | lcd.c | 390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
647 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6); integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
702 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6); integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
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| H A D | dvi.c | 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); viafb_tmds_trasmitter_identify()
435 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); viafb_dvi_enable()
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| H A D | hw.c | 1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); viafb_init_dac()
1695 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); viafb_init_dac()
2048 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); enable_second_display_channel()
2050 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); enable_second_display_channel()
2056 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); disable_second_display_channel()
2058 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); disable_second_display_channel()
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| H A D | share.h | 34 #define BIT6 0x40 macro
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| /linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/ |
| H A D | r8192E_hw.h | 232 #define IMR_MGNTDOK BIT6
247 #define TPPoll_MQ BIT6
287 #define AcmHw_VoqStatus BIT6
377 #define RRSR_12M BIT6
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| /linux-4.4.14/drivers/staging/rtl8192e/ |
| H A D | rtl819x_Qos.h | 24 #define BIT6 0x00000040 macro
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| H A D | pwrseq.h | 307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
442 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
466 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6 \
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
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| /linux-4.4.14/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 299 #define IRQ_EXITHUNT BIT6 // receive frame start
300 #define IRQ_RXTIME BIT6 // rx char timeout
307 #define XFW BIT6 // transmit FIFO write enable
679 #define CMD_RXRESET BIT6 // receiver reset
925 // BIT6:framing error rx_ready_async()
927 if (status & (BIT7 + BIT6)) { rx_ready_async()
941 else if (status & BIT6) rx_ready_async()
1483 info->read_status_mask |= BIT7 | BIT6; mgslpc_change_params()
1485 info->ignore_status_mask |= BIT7 | BIT6; mgslpc_change_params()
2191 set_reg_bits(info, CHA+DAFO, BIT6); mgslpc_break()
2193 clear_reg_bits(info, CHA+DAFO, BIT6); mgslpc_break()
3183 val |= BIT6; hdlc_mode()
3186 val |= BIT6; hdlc_mode()
3189 val |= BIT7 | BIT6; hdlc_mode()
3273 clear_reg_bits(info, CHA + CCR0, BIT6); hdlc_mode()
3440 val |= BIT6; async_mode()
3623 val &= ~BIT6; set_signals()
3625 val |= BIT6; set_signals()
3682 else if (status & BIT6) rx_get_frame()
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| /linux-4.4.14/drivers/scsi/ |
| H A D | dc395x.h | 69 #define BIT6 0x00000040 macro
137 #define DATAIN BIT6
179 #define EN_ATN_STOP BIT6
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| /linux-4.4.14/drivers/tty/ |
| H A D | synclinkmp.c | 416 #define RXINTE BIT6
422 #define IDLE BIT6
435 #define PMP BIT6
436 #define SHRT BIT6
2344 * BIT6 = EOM (end of message/frame) isr_rxdmaok()
2600 if (timerstatus0 & (BIT7 | BIT6)) synclinkmp_interrupt()
2604 if (timerstatus1 & (BIT7 | BIT6)) synclinkmp_interrupt()
4439 RegValue=BIT6; async_mode()
4448 RegValue=BIT6; async_mode()
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ hdlc_mode()
4604 RegValue |= BIT6; hdlc_mode()
4606 RegValue |= BIT6 + BIT5; hdlc_mode()
4617 RegValue |= BIT6; hdlc_mode()
4619 RegValue |= BIT6 + BIT5; hdlc_mode()
4921 status |= BIT6; rx_get_frame()
4923 if (status & (BIT6+BIT5+BIT3+BIT2)) { rx_get_frame()
4927 if (status & BIT6) rx_get_frame()
5104 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4)); irq_test()
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| H A D | synclink_gt.c | 421 #define IRQ_CTS BIT6
1415 value |= BIT6; set_break()
1417 value &= ~BIT6; set_break()
4017 wr_reg32(info, RDCSR, BIT6); rx_start()
4030 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); rx_start()
4327 val |= BIT6; sync_mode()
4419 val |= BIT6 + BIT5; /* 011, txclk = BRG/16 */ sync_mode()
4421 val |= BIT6; /* 010, txclk = BRG */ sync_mode()
4450 val = BIT7 + BIT6; break; sync_mode()
4451 default: val = BIT6; // NRZ encodings sync_mode()
4504 tcr = (tcr & ~(BIT6 + BIT5)) | BIT4; tx_set_idle()
4507 } else if (!(tcr & BIT6)) { tx_set_idle()
4574 val |= BIT7 + BIT6 + BIT5; /* 1110 */ msc_set_vcr()
4577 val |= BIT6; /* 0100 */ msc_set_vcr()
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| H A D | synclink.c | 506 #define RXSTATUS_IDLE_RECEIVED BIT6
546 #define TXSTATUS_IDLE_SENT BIT6
567 #define MISCSTATUS_DCD BIT6
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
627 #define TXSTATUS_IDLE_SENT BIT6
5211 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); usc_enable_loopback()
5250 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); usc_enable_loopback()
5920 RegValue |= BIT6; usc_set_async_mode()
5977 RegValue |= BIT6; usc_set_async_mode()
6268 Control &= ~(BIT6); usc_set_serial_signals()
6270 Control |= BIT6; usc_set_serial_signals()
7282 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { mgsl_dma_test()
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| /linux-4.4.14/include/uapi/linux/ |
| H A D | synclink.h | 24 #define BIT6 0x0040 macro
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| /linux-4.4.14/drivers/tty/serial/ |
| H A D | ip22zilog.h | 153 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| H A D | sunzilog.h | 155 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| H A D | zs.h | 172 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| H A D | pmac_zilog.h | 246 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.4.14/drivers/net/hamradio/ |
| H A D | z8530.h | 117 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.4.14/drivers/net/wan/ |
| H A D | z85230.h | 138 #define BIT6 1 /* 6 bit/8bit sync */ macro
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| H A D | reg.h | 390 #define RRSR_12M BIT6
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| /linux-4.4.14/drivers/misc/altera-stapl/ |
| H A D | altera.c | 485 * BIT6 - FORCED OFF altera_execute()
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| /linux-4.4.14/drivers/scsi/lpfc/ |
| H A D | lpfc_hw4.h | 680 #define LPFC_SLI4_INTR6 BIT6
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