Lines Matching refs:BIT6
506 #define RXSTATUS_IDLE_RECEIVED BIT6
546 #define TXSTATUS_IDLE_SENT BIT6
567 #define MISCSTATUS_DCD BIT6
591 #define SICR_DCD_INACTIVE BIT6
592 #define SICR_DCD (BIT7|BIT6)
627 #define TXSTATUS_IDLE_SENT BIT6
5211 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); in usc_enable_loopback()
5250 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); in usc_enable_loopback()
5920 RegValue |= BIT6; in usc_set_async_mode()
5977 RegValue |= BIT6; in usc_set_async_mode()
6268 Control &= ~(BIT6); in usc_set_serial_signals()
6270 Control |= BIT6; in usc_set_serial_signals()
7282 while ( !(status & (BIT6 | BIT5 | BIT4 | BIT2 | BIT1)) ) { in mgsl_dma_test()