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Searched refs:ARC_REG_TLBPD0 (Results 1 – 3 of 3) sorted by relevance

/linux-4.4.14/arch/arc/include/asm/
Dmmu.h25 #define ARC_REG_TLBPD0 0x405 macro
33 #define ARC_REG_TLBPD0 0x460 macro
/linux-4.4.14/arch/arc/mm/
Dtlb.c116 write_aux_reg(ARC_REG_TLBPD0, 0); in __tlb_entry_erase()
126 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid); in tlb_entry_lkup()
228 write_aux_reg(ARC_REG_TLBPD0, vaddr_n_asid | _PAGE_PRESENT); in tlb_entry_erase()
234 write_aux_reg(ARC_REG_TLBPD0, pd0); in tlb_entry_insert()
264 write_aux_reg(ARC_REG_TLBPD0, 0); in local_flush_tlb_all()
276 write_aux_reg(ARC_REG_TLBPD0, _PAGE_HW_SZ); in local_flush_tlb_all()
901 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()
Dtlbex.S274 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
277 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0