Searched refs:wr_reg32 (Results 1 - 4 of 4) sorted by relevance
/linux-4.1.27/drivers/crypto/caam/ |
H A D | jr.c | 37 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); caam_reset_hw_jr() 50 wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET); caam_reset_hw_jr() 153 wr_reg32(&jrp->rregs->jrintstatus, irqstate); caam_jr_interrupt() 206 wr_reg32(&jrp->rregs->outring_rmvd, 1); caam_jr_dequeue() 360 wr_reg32(&jrp->rregs->inpring_jobadd, 1); caam_jr_enqueue() 421 wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH); caam_jr_init() 422 wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH); caam_jr_init()
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H A D | ctrl.c | 113 wr_reg32(&deco->descbuf[i], *(desc + i)); run_descriptor_deco0() 124 wr_reg32(&deco->jr_ctl_hi, flags); run_descriptor_deco0() 348 wr_reg32(&r4tst->rtsdctl, val); kick_trng() 350 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); kick_trng() 352 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); kick_trng() 363 wr_reg32(&r4tst->rtmctl, val); kick_trng() 534 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
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H A D | regs.h | 69 #define wr_reg32(reg, data) out_be32(reg, data) macro 77 #define wr_reg32(reg, data) __raw_writel(data, reg) macro 90 wr_reg32((u32 __iomem *)reg, (data & 0xffffffff00000000ull) >> 32); wr_reg64() 91 wr_reg32((u32 __iomem *)reg + 1, data & 0x00000000ffffffffull); wr_reg64() 103 wr_reg32((u32 __iomem *)reg + 1, (data & 0xffffffff00000000ull) >> 32); wr_reg64() 104 wr_reg32((u32 __iomem *)reg, data & 0x00000000ffffffffull); wr_reg64()
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/linux-4.1.27/drivers/tty/ |
H A D | synclink_gt.c | 437 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value); 2231 wr_reg32(info, RDCSR, status); /* clear pending */ isr_rdma() 2256 wr_reg32(info, TDCSR, status); /* clear pending */ isr_tdma() 2402 wr_reg32(info, IOSR, changed); slgt_interrupt() 2926 wr_reg32(info, XSR, xsync); set_xsync() 2963 wr_reg32(info, XCR, xctrl); set_xctrl() 2996 wr_reg32(info, IODR, data); set_gpio() 3002 wr_reg32(info, IOVR, data); set_gpio() 3107 wr_reg32(info, IOER, rd_reg32(info, IOER) | gpio.smask); wait_gpio() 3129 wr_reg32(info, IOER, 0); wait_gpio() 3896 static void wr_reg32(struct slgt_info *info, unsigned int addr, __u32 value) wr_reg32() function 3907 wr_reg32(info, RDCSR, BIT1); rdma_reset() 3920 wr_reg32(info, TDCSR, BIT1); tdma_reset() 4022 wr_reg32(info, RDCSR, BIT6); rx_start() 4028 wr_reg32(info, RDDAR, info->rbufs[0].pdesc); rx_start() 4032 wr_reg32(info, RDCSR, (BIT2 + BIT0)); rx_start() 4035 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); rx_start() 4080 wr_reg32(info, TDDAR, info->tbufs[info->tbuf_start].pdesc); tx_start() 4081 wr_reg32(info, TDCSR, BIT2 + BIT0); tx_start()
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