Searched refs:vlv_dpio_write (Results 1 – 5 of 5) sorted by relevance
/linux-4.1.27/drivers/gpu/drm/i915/ |
D | intel_hdmi.c | 1299 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_hdmi_pre_enable() 1302 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0); in vlv_hdmi_pre_enable() 1303 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f); in vlv_hdmi_pre_enable() 1304 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a); in vlv_hdmi_pre_enable() 1305 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040); in vlv_hdmi_pre_enable() 1306 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878); in vlv_hdmi_pre_enable() 1307 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in vlv_hdmi_pre_enable() 1308 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000); in vlv_hdmi_pre_enable() 1309 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); in vlv_hdmi_pre_enable() 1312 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_hdmi_pre_enable() [all …]
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D | intel_dp.c | 2355 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_post_disable_dp() 2359 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_post_disable_dp() 2363 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_post_disable_dp() 2367 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_post_disable_dp() 2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_pre_enable_dp() 2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_pre_enable_dp() 2674 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_pre_enable_dp() 2695 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_dp_pre_pll_enable() 2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_dp_pre_pll_enable() 2705 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_dp_pre_pll_enable() [all …]
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D | intel_sideband.c | 205 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) in vlv_dpio_write() function
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D | intel_display.c | 1640 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); in chv_enable_pll() 1807 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); in chv_disable_pll() 1813 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_disable_pll() 1817 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_disable_pll() 6104 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp() 6109 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp() 6113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); in vlv_pllb_recal_opamp() 6118 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); in vlv_pllb_recal_opamp() 6241 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); in vlv_prepare_pll() 6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); in vlv_prepare_pll() [all …]
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D | i915_drv.h | 3159 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
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