Lines Matching refs:vlv_dpio_write
2355 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_post_disable_dp()
2359 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_post_disable_dp()
2363 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_post_disable_dp()
2367 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_post_disable_dp()
2672 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); in vlv_pre_enable_dp()
2673 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); in vlv_pre_enable_dp()
2674 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); in vlv_pre_enable_dp()
2695 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), in vlv_dp_pre_pll_enable()
2698 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), in vlv_dp_pre_pll_enable()
2705 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); in vlv_dp_pre_pll_enable()
2706 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); in vlv_dp_pre_pll_enable()
2707 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); in vlv_dp_pre_pll_enable()
2729 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); in chv_pre_enable_dp()
2733 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); in chv_pre_enable_dp()
2738 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); in chv_pre_enable_dp()
2742 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); in chv_pre_enable_dp()
2746 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); in chv_pre_enable_dp()
2750 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); in chv_pre_enable_dp()
2756 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), in chv_pre_enable_dp()
2791 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); in chv_dp_pre_pll_enable()
2799 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); in chv_dp_pre_pll_enable()
2809 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); in chv_dp_pre_pll_enable()
2817 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); in chv_dp_pre_pll_enable()
2829 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); in chv_dp_pre_pll_enable()
3055 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); in intel_vlv_signal_levels()
3056 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); in intel_vlv_signal_levels()
3057 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), in intel_vlv_signal_levels()
3059 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); in intel_vlv_signal_levels()
3060 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); in intel_vlv_signal_levels()
3061 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); in intel_vlv_signal_levels()
3062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000); in intel_vlv_signal_levels()
3157 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in intel_chv_signal_levels()
3163 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in intel_chv_signal_levels()
3168 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in intel_chv_signal_levels()
3173 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in intel_chv_signal_levels()
3180 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); in intel_chv_signal_levels()
3188 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in intel_chv_signal_levels()
3195 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in intel_chv_signal_levels()
3212 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); in intel_chv_signal_levels()
3219 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); in intel_chv_signal_levels()
3226 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in intel_chv_signal_levels()
3230 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in intel_chv_signal_levels()
3235 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val); in intel_chv_signal_levels()