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Searched refs:vlv_dpio_read (Results 1 – 5 of 5) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_hdmi.c1292 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_hdmi_pre_enable()
1375 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_hdmi_pre_pll_enable()
1383 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_hdmi_pre_pll_enable()
1393 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); in chv_hdmi_pre_pll_enable()
1401 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); in chv_hdmi_pre_pll_enable()
1414 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); in chv_hdmi_pre_pll_enable()
1454 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_hdmi_post_disable()
1458 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_hdmi_post_disable()
1462 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_hdmi_post_disable()
1466 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_hdmi_post_disable()
[all …]
Dintel_dp.c2353 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_post_disable_dp()
2357 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_post_disable_dp()
2361 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_post_disable_dp()
2365 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); in chv_post_disable_dp()
2665 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); in vlv_pre_enable_dp()
2727 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); in chv_pre_enable_dp()
2731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); in chv_pre_enable_dp()
2736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); in chv_pre_enable_dp()
2740 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); in chv_pre_enable_dp()
2744 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); in chv_pre_enable_dp()
[all …]
Dintel_sideband.c188 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) in vlv_dpio_read() function
Dintel_display.c1638 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_enable_pll()
1805 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); in chv_disable_pll()
1811 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); in chv_disable_pll()
1815 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); in chv_disable_pll()
6101 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6111 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); in vlv_pllb_recal_opamp()
6115 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); in vlv_pllb_recal_opamp()
6244 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); in vlv_prepare_pll()
6296 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); in vlv_prepare_pll()
[all …]
Di915_drv.h3158 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);