1638 	tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in chv_enable_pll()
1805 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));  in chv_disable_pll()
1811 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);  in chv_disable_pll()
1815 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);  in chv_disable_pll()
6101 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
6106 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
6111 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));  in vlv_pllb_recal_opamp()
6115 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);  in vlv_pllb_recal_opamp()
6244 	reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));  in vlv_prepare_pll()
6296 	coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));  in vlv_prepare_pll()
6371 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));  in chv_prepare_pll()
6379 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));  in chv_prepare_pll()
6412 	dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));  in chv_prepare_pll()
6419 			vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |  in chv_prepare_pll()
6924 	mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));  in vlv_crtc_clock_get()
7020 	cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));  in chv_crtc_clock_get()
7021 	pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));  in chv_crtc_clock_get()
7022 	pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));  in chv_crtc_clock_get()
7023 	pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));  in chv_crtc_clock_get()